From e15e33433e7c05111968dc9b434a52fd42cbd221 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 30 Nov 2007 07:15:41 +0100 Subject: ppc4xx: Kilauea: Add PCIe reset assertion upon power-up This manual PCIe reset triggering solves the problem seen with the Intel EPRO/1000 card, which was not detected (link not established) upon power-up reset. Signed-off-by: Stefan Roese --- board/amcc/kilauea/kilauea.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'board/amcc/kilauea') diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 09b7382c4e..36e9e4a211 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -37,14 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -void fpga_init(void) -{ - /* - * Set FPGA regs - */ - out32(CFG_FPGA_BASE, 0xff570cc0); -} - /* * Board early initialization function */ @@ -199,7 +191,12 @@ int board_early_init_f (void) */ mtsdr(SDR0_SRST, 0); - fpga_init(); + /* + * Configure FPGA register with PCIe reset + */ + out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */ + mdelay(50); + out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */ /* Configure 405EX for NAND usage */ val = SDR0_CUST0_MUX_NDFC_SEL | -- cgit v1.2.1