From 84a7562e49b7168bef3a0b55c4605dea63413c0f Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Thu, 21 Jan 2016 14:57:30 +0900
Subject: ARM: uniphier: support some more DRAM use cases on PH1-Pro4 boards

Some of PH1-Pro4 boards are equipped with larger amount of DRAM than
the reference board.  Add UMC settings to support them.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/dram/umc-ph1-pro4.c | 80 ++++++++++++++++++++----------
 1 file changed, 53 insertions(+), 27 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
index 4d976e3a97..261f7cfce7 100644
--- a/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/dram/umc-ph1-pro4.c
@@ -13,6 +13,16 @@
 #include "ddrphy-regs.h"
 #include "umc-regs.h"
 
+enum dram_size {
+	DRAM_SZ_128M,
+	DRAM_SZ_256M,
+	DRAM_SZ_512M,
+	DRAM_SZ_NR,
+};
+
+static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f};
+static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
+
 static void umc_start_ssif(void __iomem *ssif_base)
 {
 	writel(0x00000001, ssif_base + 0x0000b004);
@@ -56,19 +66,36 @@ static void umc_start_ssif(void __iomem *ssif_base)
 	writel(0x00000001, ssif_base + UMC_DMDRST);
 }
 
-static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
-			      int size, int freq)
+static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
+			     int size, int width)
 {
+	enum dram_size dram_size;
+
+	switch (size / (width / 16)) {
+	case SZ_128M:
+		dram_size = DRAM_SZ_128M;
+		break;
+	case SZ_256M:
+		dram_size = DRAM_SZ_256M;
+		break;
+	case SZ_512M:
+		dram_size = DRAM_SZ_512M;
+		break;
+	default:
+		printf("unsupported DRAM size\n");
+		return -EINVAL;
+	}
+
 	writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
 	writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
 	writel(0x5101387f, dramcont + UMC_INITCTLA);
-	writel(0x43030d3f, dramcont + UMC_INITCTLB);
+	writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB);
 	writel(0x00ff00ff, dramcont + UMC_INITCTLC);
 	writel(0x00000d71, dramcont + UMC_DRMMR0);
 	writel(0x00000006, dramcont + UMC_DRMMR1);
 	writel(0x00000298, dramcont + UMC_DRMMR2);
 	writel(0x00000000, dramcont + UMC_DRMMR3);
-	writel(0x003f0617, dramcont + UMC_SPCCTLA);
+	writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
 	writel(0x00ff0008, dramcont + UMC_SPCCTLB);
 	writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
 	writel(0x000c00ae, dramcont + UMC_RDATACTL_D1);
@@ -90,9 +117,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
 	writel(0x200a0a00, dramcont + UMC_SPCSETB);
 	writel(0x00010000, dramcont + UMC_SPCSETD);
 	writel(0x80000020, dramcont + UMC_DFICUPDCTLA);
+
+	return 0;
 }
 
-static int umc_init_sub(int freq, int size_ch0, int size_ch1)
+int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
 {
 	void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE;
 	void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0);
@@ -103,6 +132,12 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
 	void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1);
 	void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0);
 	void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1);
+	int ret;
+
+	if (bd->dram_freq != 1600) {
+		pr_err("Unsupported DDR configuration\n");
+		return -EINVAL;
+	}
 
 	umc_dram_init_start(dramcont0);
 	umc_dram_init_start(dramcont1);
@@ -111,52 +146,43 @@ static int umc_init_sub(int freq, int size_ch0, int size_ch1)
 
 	writel(0x00000101, dramcont0 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0);
+	ph1_pro4_ddrphy_init(phy0_0, bd->dram_freq, bd->dram_ch0_size);
 
 	ddrphy_prepare_training(phy0_0, 0);
 	ddrphy_training(phy0_0);
 
 	writel(0x00000103, dramcont0 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0);
+	ph1_pro4_ddrphy_init(phy0_1, bd->dram_freq, bd->dram_ch0_size);
 
 	ddrphy_prepare_training(phy0_1, 1);
 	ddrphy_training(phy0_1);
 
 	writel(0x00000101, dramcont1 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1);
+	ph1_pro4_ddrphy_init(phy1_0, bd->dram_freq, bd->dram_ch1_size);
 
 	ddrphy_prepare_training(phy1_0, 0);
 	ddrphy_training(phy1_0);
 
 	writel(0x00000103, dramcont1 + UMC_DIOCTLA);
 
-	ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1);
+	ph1_pro4_ddrphy_init(phy1_1, bd->dram_freq, bd->dram_ch1_size);
 
 	ddrphy_prepare_training(phy1_1, 1);
 	ddrphy_training(phy1_1);
 
-	umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq);
-	umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq);
+	ret = umc_dramcont_init(dramcont0, ca_base0, bd->dram_ch0_size,
+				bd->dram_ch0_width);
+	if (ret)
+		return ret;
+
+	ret = umc_dramcont_init(dramcont1, ca_base1, bd->dram_ch1_size,
+				bd->dram_ch1_width);
+	if (ret)
+		return ret;
 
 	umc_start_ssif(ssif_base);
 
 	return 0;
 }
-
-int ph1_pro4_umc_init(const struct uniphier_board_data *bd)
-{
-	if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) ||
-	     (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) &&
-	    ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) ||
-	     (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) &&
-	    bd->dram_freq == 1600) {
-		return umc_init_sub(bd->dram_freq,
-				    bd->dram_ch0_size / SZ_128M,
-				    bd->dram_ch1_size / SZ_128M);
-	} else {
-		pr_err("Unsupported DDR configuration\n");
-		return -EINVAL;
-	}
-}
-- 
cgit v1.2.1


From 494456bc674d8543bd8d4dcf47347a0cc992d87c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 19:12:31 +0900
Subject: spl: define BOOT_DEVICE_USB

This enum is referenced from common/spl/spl.c.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/include/asm/spl.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'arch')

diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h
index 5c5d33f0bd..19c38f4083 100644
--- a/arch/arm/include/asm/spl.h
+++ b/arch/arm/include/asm/spl.h
@@ -24,6 +24,7 @@ enum {
 	BOOT_DEVICE_NOR,
 	BOOT_DEVICE_UART,
 	BOOT_DEVICE_SPI,
+	BOOT_DEVICE_USB,
 	BOOT_DEVICE_SATA,
 	BOOT_DEVICE_I2C,
 	BOOT_DEVICE_BOARD,
-- 
cgit v1.2.1


From 755c7d9a6179ffb15829da34cbc818d7fb4de558 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:28 +0900
Subject: ARM: uniphier: change stack pointer address for SPL

No special reason for the current stack address 0x0ff08000.
Change it to 0x00100000 to simplify the init_page_table.

There are two types of SoCs in terms of the load address of SPL.

 [1] PH1-sLD3, PH1-LD4, PH1-sLD8
   SPL is loaded at 0x00040000-0x0004ffff
 [2] PH1-Pro4, PH1-Pro5, ProXstream2, PH1-LD6b
   SPL is loaded at 0x00100000-0x0010ffff

The new stack area (0x000f8000-0x00100000) should be safe for all the
cases.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/init_page_table.S | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
index 2d3ad15c6e..4ed2656ee9 100644
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ b/arch/arm/mach-uniphier/init_page_table.S
@@ -13,15 +13,12 @@
 #define DEVICE	0x00002002 /* Non-shareable Device */
 #define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
 
-#define TEXT_SECTION	((CONFIG_SPL_TEXT_BASE) >> (SECTION_SHIFT))
-#define STACK_SECTION	((CONFIG_SPL_STACK) >> (SECTION_SHIFT))
-
 	.section ".rodata"
 	.align 14
 ENTRY(init_page_table)
 	section = 0
 	.rept NR_SECTIONS
-	.if section == 0 || section == 1 || section == STACK_SECTION
+	.if section == 0 || section == 1
 	attr = NORMAL
 	.else
 	attr = DEVICE
-- 
cgit v1.2.1


From 4b50369fb53599aca34636d3a6f70117fe38bf07 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:29 +0900
Subject: ARM: uniphier: create early page table at run-time

UniPhier SoCs are not equipped with dedicated on-chip SRAM.  Instead,
locked outer cache is used as RAM area during the early boot stage
where DRAM is not ready yet.  This effectively means MMU must be
always enabled while we are in SPL.

Currently, the SPL image for UniPhier SoCs contains the page table
statically defined at compile time.  It has been a burden because the
16KB page table occupies a quarter memory footprint of the 64KB SPL
image.

Finally, there is no more room to implement new features in SPL.
Setting aside the NOR boot mode, this issue can be solved by creating
the page table onto RAM at run time.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/Makefile          |   1 -
 arch/arm/mach-uniphier/init_page_table.S |  29 ---------
 arch/arm/mach-uniphier/lowlevel_init.S   | 102 ++++++++++++++++++++++++++++---
 3 files changed, 94 insertions(+), 38 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/init_page_table.S

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index ea3ae5425e..491e78e415 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -5,7 +5,6 @@
 ifdef CONFIG_SPL_BUILD
 
 obj-y += lowlevel_init.o
-obj-y += init_page_table.o
 
 obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
diff --git a/arch/arm/mach-uniphier/init_page_table.S b/arch/arm/mach-uniphier/init_page_table.S
deleted file mode 100644
index 4ed2656ee9..0000000000
--- a/arch/arm/mach-uniphier/init_page_table.S
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-
-/* page table */
-#define NR_SECTIONS	4096
-#define SECTION_SHIFT	20
-#define DEVICE	0x00002002 /* Non-shareable Device */
-#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
-
-	.section ".rodata"
-	.align 14
-ENTRY(init_page_table)
-	section = 0
-	.rept NR_SECTIONS
-	.if section == 0 || section == 1
-	attr = NORMAL
-	.else
-	attr = DEVICE
-	.endif
-	.word (section << SECTION_SHIFT) | attr
-	section = section + 1
-	.endr
-END(init_page_table)
diff --git a/arch/arm/mach-uniphier/lowlevel_init.S b/arch/arm/mach-uniphier/lowlevel_init.S
index 291337070e..dd03ad8143 100644
--- a/arch/arm/mach-uniphier/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/lowlevel_init.S
@@ -29,12 +29,16 @@ ENTRY(lowlevel_init)
 	bl	debug_ll_init
 #endif
 
+	bl	setup_init_ram		@ RAM area for stack and page talbe
+
 	/*
 	 * Now we are using the page table embedded in the Boot ROM.
 	 * It is not handy since it is not a straight mapped table for sLD3.
-	 * What we need to do next is to switch over to the page table in SPL.
+	 * Also, the access to the external bus is prohibited.  What we need
+	 * to do next is to create a page table and switch over to it.
 	 */
-	ldr	r3, =init_page_table	@ page table must be 16KB aligned
+	bl	create_page_table
+	bl	v7_flush_dcache_all
 
 	/* Disable MMU and Dcache before switching Page Table */
 	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
@@ -43,8 +47,6 @@ ENTRY(lowlevel_init)
 
 	bl	enable_mmu
 
-	bl	setup_init_ram		@ RAM area for temporary stack pointer
-
 	mov	lr, r8			@ restore link
 	mov	pc, lr			@ back to my caller
 ENDPROC(lowlevel_init)
@@ -55,7 +57,7 @@ ENTRY(enable_mmu)
 	orr	r0, r0, #0x20		@ disable TTBR1
 	mcr	p15, 0, r0, c2, c0, 2
 
-	orr	r0, r3, #0x8		@ Outer Cacheability for table walks: WBWA
+	orr	r0, r12, #0x8		@ Outer Cacheability for table walks: WBWA
 	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0
 
 	mov	r0, #0
@@ -82,8 +84,9 @@ ENDPROC(enable_mmu)
  * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
  * It is large enough for tmp RAM.
  */
-#define BOOT_RAM_SIZE    (SZ_32K)
-#define BOOT_WAY_BITS    (0x00000100)   /* way 8 */
+#define BOOT_RAM_SIZE	(SZ_32K)
+#define BOOT_RAM_BASE	((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
+#define BOOT_WAY_BITS	(0x00000100)   /* way 8 */
 
 ENTRY(setup_init_ram)
 	/*
@@ -96,7 +99,7 @@ ENTRY(setup_init_ram)
 	ldr	r0, = 0x00408006	@ touch to zero with address range
 	ldr	r1, = SSCOQM
 	str	r0, [r1]
-	ldr	r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE)	@ base address
+	ldr	r0, = BOOT_RAM_BASE
 	ldr	r1, = SSCOQAD
 	str	r0, [r1]
 	ldr	r0, = BOOT_RAM_SIZE
@@ -119,3 +122,86 @@ ENTRY(setup_init_ram)
 
 	mov	pc, lr
 ENDPROC(setup_init_ram)
+
+#define DEVICE	0x00002002 /* Non-shareable Device */
+#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
+
+ENTRY(create_page_table)
+	ldr	r0, = DEVICE
+	ldr	r1, = BOOT_RAM_BASE
+	mov	r12, r1			@ r12 is preserved during D-cache flush
+0:	str	r0, [r1], #4		@ specify all the sections as Device
+	adds	r0, r0, #0x00100000
+	bcc	0b
+
+	ldr	r0, = NORMAL
+	str	r0, [r12]		@ mark the first section as Normal
+	add	r0, r0, #0x00100000
+	str	r0, [r12, #4]		@ mark the second section as Normal
+	mov	pc, lr
+ENDPROC(create_page_table)
+
+/* We don't use Thumb instructions for now */
+#define ARM(x...)	x
+#define THUMB(x...)
+
+/*
+ *	v7_flush_dcache_all()
+ *
+ *	Flush the whole D-cache.
+ *
+ *	Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
+ *
+ *	- mm    - mm_struct describing address space
+ *
+ *	Note: copied from arch/arm/mm/cache-v7.S of Linux 4.4
+ */
+ENTRY(v7_flush_dcache_all)
+	dmb					@ ensure ordering with previous memory accesses
+	mrc	p15, 1, r0, c0, c0, 1		@ read clidr
+	mov	r3, r0, lsr #23			@ move LoC into position
+	ands	r3, r3, #7 << 1			@ extract LoC*2 from clidr
+	beq	finished			@ if loc is 0, then no need to clean
+start_flush_levels:
+	mov	r10, #0				@ start clean at cache level 0
+flush_levels:
+	add	r2, r10, r10, lsr #1		@ work out 3x current cache level
+	mov	r1, r0, lsr r2			@ extract cache type bits from clidr
+	and	r1, r1, #7			@ mask of the bits for current cache only
+	cmp	r1, #2				@ see what cache we have at this level
+	blt	skip				@ skip if no cache, or just i-cache
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	isb					@ isb to sych the new cssr&csidr
+	mrc	p15, 1, r1, c0, c0, 0		@ read the new csidr
+	and	r2, r1, #7			@ extract the length of the cache lines
+	add	r2, r2, #4			@ add 4 (line length offset)
+	movw	r4, #0x3ff
+	ands	r4, r4, r1, lsr #3		@ find maximum number on the way size
+	clz	r5, r4				@ find bit position of way size increment
+	movw	r7, #0x7fff
+	ands	r7, r7, r1, lsr #13		@ extract max number of the index size
+loop1:
+	mov	r9, r7				@ create working copy of max index
+loop2:
+ ARM(	orr	r11, r10, r4, lsl r5	)	@ factor way and cache number into r11
+ THUMB(	lsl	r6, r4, r5		)
+ THUMB(	orr	r11, r10, r6		)	@ factor way and cache number into r11
+ ARM(	orr	r11, r11, r9, lsl r2	)	@ factor index number into r11
+ THUMB(	lsl	r6, r9, r2		)
+ THUMB(	orr	r11, r11, r6		)	@ factor index number into r11
+	mcr	p15, 0, r11, c7, c14, 2		@ clean & invalidate by set/way
+	subs	r9, r9, #1			@ decrement the index
+	bge	loop2
+	subs	r4, r4, #1			@ decrement the way
+	bge	loop1
+skip:
+	add	r10, r10, #2			@ increment cache number
+	cmp	r3, r10
+	bgt	flush_levels
+finished:
+	mov	r10, #0				@ swith back to cache level 0
+	mcr	p15, 2, r10, c0, c0, 0		@ select current cache level in cssr
+	dsb	st
+	isb
+	mov	pc, lr
+ENDPROC(v7_flush_dcache_all)
-- 
cgit v1.2.1


From a89be270e7eb42fca6c77bb25bd77971569f31ee Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:30 +0900
Subject: ARM: uniphier: add missing static qualifier

This function is for local use in the file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
index de12953585..3769ec555b 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -46,7 +46,7 @@ static struct boot_device_info boot_device_table[] = {
 	{BOOT_DEVICE_NONE, "Reserved"},
 };
 
-int get_boot_mode_sel(void)
+static int get_boot_mode_sel(void)
 {
 	return (readl(SG_PINMON0) >> 1) & 0x1f;
 }
-- 
cgit v1.2.1


From fec4816387a978e651da74c83bcdd5019a6d024c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:31 +0900
Subject: ARM: uniphier: support USB boot mode for ProXstream2 / PH1-LD6b SoC

The USB boot code is too fat and complicated to be included in SPL
(at least for now).  So, it was implemented as a separate project
(what we call USB-loader).

The expected boot sequence is as follows:

  Boot ROM -> USB-loader -> SPL -> U-Boot proper

The USB-loader loads the SPL and U-Boot proper from a USB memory
onto the locked L2 cache.  Then, SPL needs to copy the U-Boot proper
to DRAM, so this mode looks like a NOR boot from the view of SPL.
However, we want to distinguish between (genuine) NOR boot and USB
boot in some places.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/board_late_init.c                 |  8 +++++++-
 arch/arm/mach-uniphier/boot-mode/boot-device.h           |  2 ++
 arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c |  3 +++
 arch/arm/mach-uniphier/boot-mode/boot-mode.c             | 11 ++++++++++-
 4 files changed, 22 insertions(+), 2 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index c2a32618ac..eba48a248d 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -11,6 +11,8 @@
 #include <linux/io.h>
 #include <../drivers/mtd/nand/denali.h>
 
+#include "boot-mode/boot-device.h"
+
 static void nand_denali_wp_disable(void)
 {
 #ifdef CONFIG_NAND_DENALI
@@ -62,7 +64,7 @@ int board_late_init(void)
 {
 	puts("MODE:  ");
 
-	switch (spl_boot_device()) {
+	switch (spl_boot_device_raw()) {
 	case BOOT_DEVICE_MMC1:
 		printf("eMMC Boot\n");
 		setenv("bootmode", "emmcboot");
@@ -76,6 +78,10 @@ int board_late_init(void)
 		printf("NOR Boot\n");
 		setenv("bootmode", "norboot");
 		break;
+	case BOOT_DEVICE_USB:
+		printf("USB Boot\n");
+		setenv("bootmode", "usbboot");
+		break;
 	default:
 		printf("Unsupported Boot Mode\n");
 		return -1;
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h
index 2ab5a535fa..1c59aaa606 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h
@@ -22,4 +22,6 @@ void ph1_ld4_boot_mode_show(void);
 void ph1_pro5_boot_mode_show(void);
 void proxstream2_boot_mode_show(void);
 
+u32 spl_boot_device_raw(void);
+
 #endif /* _ASM_BOOT_DEVICE_H_ */
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
index 3769ec555b..1b0c183808 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-proxstream2.c
@@ -55,6 +55,9 @@ u32 proxstream2_boot_device(void)
 {
 	int boot_mode;
 
+	if (readl(SG_PINMON0) & BIT(6))
+		return BOOT_DEVICE_USB;
+
 	boot_mode = get_boot_mode_sel();
 
 	return boot_device_table[boot_mode].type;
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
index 0c5749badb..935e551472 100644
--- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c
+++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c
@@ -11,7 +11,7 @@
 #include "../soc-info.h"
 #include "boot-device.h"
 
-u32 spl_boot_device(void)
+u32 spl_boot_device_raw(void)
 {
 	if (boot_is_swapped())
 		return BOOT_DEVICE_NOR;
@@ -43,3 +43,12 @@ u32 spl_boot_device(void)
 		return BOOT_DEVICE_NONE;
 	}
 }
+
+u32 spl_boot_device(void)
+{
+	u32 ret;
+
+	ret = spl_boot_device_raw();
+
+	return ret == BOOT_DEVICE_USB ? BOOT_DEVICE_NOR : ret;
+}
-- 
cgit v1.2.1


From 48264d9beba2ccc18b9497944048eea135883529 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:32 +0900
Subject: clk: uniphier: add Media I/O clock driver for UniPhier SoCs

This is the initial commit for the UniPhier clock drivers.
Currently, only the Media I/O clock is supported.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'arch')

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d2dbb1a5c2..d8b63e9407 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -689,6 +689,7 @@ config TARGET_COLIBRI_PXA270
 
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
+	select CLK_UNIPHIER
 	select CPU_V7
 	select SUPPORT_SPL
 	select SPL
-- 
cgit v1.2.1


From cc33609546e1e4c6c7bb59026eca7463765be61e Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:33 +0900
Subject: ARM: dts: uniphier: add reference clock nodes

Add master clock nodes generated by crystal oscillators.

  PH1-sLD3, PH1-LD4: 24.576 MHz
  PH1-Pro4, ProXstream2: 25.000 MHz
  PH1-Pro5: 20.000 MHz

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-common32.dtsi    | 7 +++++++
 arch/arm/dts/uniphier-ph1-ld4.dtsi     | 4 ++++
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 4 ++++
 arch/arm/dts/uniphier-ph1-pro5.dtsi    | 4 ++++
 arch/arm/dts/uniphier-ph1-sld3.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi    | 4 ++++
 arch/arm/dts/uniphier-proxstream2.dtsi | 4 ++++
 7 files changed, 33 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index 5d4b2cf4c3..de04de1111 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -9,6 +9,13 @@
 /include/ "skeleton.dtsi"
 
 / {
+	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+		};
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 856c207b13..6f15978a8d 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -136,6 +136,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <24576000>;
+};
+
 &serial0 {
 	clock-frequency = <36864000>;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 244ccf67e6..a236dbc13f 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -177,6 +177,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial0 {
 	clock-frequency = <73728000>;
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 00491062fe..120767c7fa 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -171,6 +171,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <20000000>;
+};
+
 &serial0 {
 	clock-frequency = <73728000>;
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index f481521a0f..9ff9584991 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -30,6 +30,12 @@
 	};
 
 	clocks {
+		refclk: ref {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24576000>;
+		};
+
 		arm_timer_clk: arm_timer_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index cb28bc4508..e765a4bb07 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -136,6 +136,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial0 {
 	clock-frequency = <80000000>;
 };
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 3ba6a4ae51..c7423ff9b6 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -182,6 +182,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial0 {
 	clock-frequency = <88900000>;
 };
-- 
cgit v1.2.1


From 233812a64274e80f1a7b291653fa9d341a326ebd Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:34 +0900
Subject: ARM: dts: uniphier: add device nodes for System Control blocks

These are mainly used for controlling clocks and resets.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-common32.dtsi    | 8 ++++++++
 arch/arm/dts/uniphier-ph1-ld4.dtsi     | 4 ++++
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 4 ++++
 arch/arm/dts/uniphier-ph1-pro5.dtsi    | 4 ++++
 arch/arm/dts/uniphier-ph1-sld3.dtsi    | 8 ++++++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi    | 4 ++++
 arch/arm/dts/uniphier-proxstream2.dtsi | 4 ++++
 7 files changed, 36 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index de04de1111..d3e5a74d79 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -101,6 +101,14 @@
 			reg = <0x5f801000 0xe00>;
 		};
 
+		sysctrl: sysctrl@61840000 {
+			/* specify compatible in each SoC DTSI */
+			reg = <0x61840000 0x4000>;
+			#clock-cells = <1>;
+			clock-names = "ref";
+			clocks = <&refclk>;
+		};
+
 		nand: nand@68000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 6f15978a8d..6bd4b91eb8 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -160,3 +160,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-ld4-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index a236dbc13f..984f99ccf8 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -200,3 +200,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-pro4-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 120767c7fa..a836176168 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -194,3 +194,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-pro5-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 9ff9584991..c7a890227d 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -206,6 +206,14 @@
 			interrupts = <0 83 4>;
 		};
 
+		sysctrl: sysctrl@f1840000 {
+			compatible = "socionext,ph1-sld3-sysctrl";
+			reg = <0xf1840000 0x4000>;
+			#clock-cells = <1>;
+			clock-names = "ref";
+			clocks = <&refclk>;
+		};
+
 		nand: nand@f8000000 {
 			compatible = "denali,denali-nand-dt";
 			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index e765a4bb07..9d97fb03a0 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -160,3 +160,7 @@
 &pinctrl {
 	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,ph1-sld8-sysctrl";
+};
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index c7423ff9b6..f6f4bbec3c 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -205,3 +205,7 @@
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };
+
+&sysctrl {
+	compatible = "socionext,proxstream2-sysctrl";
+};
-- 
cgit v1.2.1


From 9fbb2f7ec619d2a0e65cf36161b177e77138239e Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:35 +0900
Subject: ARM: dts: uniphier: add device nodes for Peripheral control block

This block provides clock and reset control for peripherals such as
UART, I2C, IC card, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-common32.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-ld4.dtsi     | 6 ++++++
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-pro5.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++
 6 files changed, 36 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index d3e5a74d79..43e5bea60d 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -74,6 +74,12 @@
 			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
 		};
 
+		peri: perictrl@59820000 {
+			/* specify compatible in each SoC DTSI */
+			reg = <0x59820000 0x200>;
+			#clock-cells = <1>;
+		};
+
 		timer@60000200 {
 			compatible = "arm,cortex-a9-global-timer";
 			reg = <0x60000200 0x20>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 6bd4b91eb8..5843097ef1 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -157,6 +157,12 @@
 	clock-frequency = <36864000>;
 };
 
+&peri {
+	compatible = "socionext,ph1-ld4-perictrl";
+	clock-names = "uart", "i2c";
+	clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-ld4-pinctrl", "syscon";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 984f99ccf8..0c2f02f77b 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -197,6 +197,12 @@
 	clock-frequency = <73728000>;
 };
 
+&peri {
+	compatible = "socionext,ph1-pro4-perictrl";
+	clock-names = "uart", "fi2c";
+	clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro4-pinctrl", "syscon";
 };
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index a836176168..305114cf87 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -191,6 +191,12 @@
 	clock-frequency = <73728000>;
 };
 
+&peri {
+	compatible = "socionext,ph1-pro5-perictrl";
+	clock-names = "uart", "fi2c";
+	clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-pro5-pinctrl", "syscon";
 };
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 9d97fb03a0..7a26b4a7d2 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -157,6 +157,12 @@
 	clock-frequency = <80000000>;
 };
 
+&peri {
+	compatible = "socionext,ph1-sld8-perictrl";
+	clock-names = "uart", "i2c";
+	clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
 &pinctrl {
 	compatible = "socionext,ph1-sld8-pinctrl", "syscon";
 };
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index f6f4bbec3c..f2faf256c4 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -202,6 +202,12 @@
 	clock-frequency = <88900000>;
 };
 
+&peri {
+	compatible = "socionext,proxstream2-perictrl";
+	clock-names = "uart", "fi2c";
+	clocks = <&sysctrl 3>, <&sysctrl 4>;
+};
+
 &pinctrl {
 	compatible = "socionext,proxstream2-pinctrl", "syscon";
 };
-- 
cgit v1.2.1


From aa37aba128750fe9539cbaf80e26e002f0cca7ad Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:36 +0900
Subject: ARM: dts: uniphier: add device nodes for MIO control block

This block provides clock and reset control for MIO (Media I/O)
hardware blocks such as USB2.0, SD card, eMMC, etc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-common32.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-ld4.dtsi     | 6 ++++++
 arch/arm/dts/uniphier-ph1-pro4.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-pro5.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-ph1-sld3.dtsi    | 8 ++++++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi    | 6 ++++++
 arch/arm/dts/uniphier-proxstream2.dtsi | 6 ++++++
 7 files changed, 44 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-common32.dtsi b/arch/arm/dts/uniphier-common32.dtsi
index 43e5bea60d..59511bde94 100644
--- a/arch/arm/dts/uniphier-common32.dtsi
+++ b/arch/arm/dts/uniphier-common32.dtsi
@@ -74,6 +74,12 @@
 			reg = <0x58c00000 0x400>, <0x59800000 0x2000>;
 		};
 
+		mio: mioctrl@59810000 {
+			/* specify compatible in each SoC DTSI */
+			reg = <0x59810000 0x800>;
+			#clock-cells = <1>;
+		};
+
 		peri: perictrl@59820000 {
 			/* specify compatible in each SoC DTSI */
 			reg = <0x59820000 0x200>;
diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 5843097ef1..628a397b16 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -157,6 +157,12 @@
 	clock-frequency = <36864000>;
 };
 
+&mio {
+	compatible = "socionext,ph1-ld4-mioctrl";
+	clock-names = "stdmac", "ehci";
+	clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
 &peri {
 	compatible = "socionext,ph1-ld4-perictrl";
 	clock-names = "uart", "i2c";
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index 0c2f02f77b..bfffe9464d 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -197,6 +197,12 @@
 	clock-frequency = <73728000>;
 };
 
+&mio {
+	compatible = "socionext,ph1-pro4-mioctrl";
+	clock-names = "stdmac", "ehci";
+	clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
 &peri {
 	compatible = "socionext,ph1-pro4-perictrl";
 	clock-names = "uart", "fi2c";
diff --git a/arch/arm/dts/uniphier-ph1-pro5.dtsi b/arch/arm/dts/uniphier-ph1-pro5.dtsi
index 305114cf87..087b25a950 100644
--- a/arch/arm/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro5.dtsi
@@ -191,6 +191,12 @@
 	clock-frequency = <73728000>;
 };
 
+&mio {
+	compatible = "socionext,ph1-pro5-mioctrl";
+	clock-names = "stdmac";
+	clocks = <&sysctrl 10>;
+};
+
 &peri {
 	compatible = "socionext,ph1-pro5-perictrl";
 	clock-names = "uart", "fi2c";
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index c7a890227d..91c9ba527f 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -178,6 +178,14 @@
 			reg = <0x59800000 0x2000>;
 		};
 
+		mio: mioctrl@59810000 {
+			compatible = "socionext,ph1-sld3-mioctrl";
+			reg = <0x59810000 0x800>;
+			#clock-cells = <1>;
+			clock-names = "stdmac", "ehci";
+			clocks = <&sysctrl 10>, <&sysctrl 18>;
+		};
+
 		usb0: usb@5a800100 {
 			compatible = "socionext,uniphier-ehci", "generic-ehci";
 			status = "disabled";
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index 7a26b4a7d2..b9ef401885 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -157,6 +157,12 @@
 	clock-frequency = <80000000>;
 };
 
+&mio {
+	compatible = "socionext,ph1-sld8-mioctrl";
+	clock-names = "stdmac", "ehci";
+	clocks = <&sysctrl 10>, <&sysctrl 18>;
+};
+
 &peri {
 	compatible = "socionext,ph1-sld8-perictrl";
 	clock-names = "uart", "i2c";
diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index f2faf256c4..2d324f95a4 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -202,6 +202,12 @@
 	clock-frequency = <88900000>;
 };
 
+&mio {
+	compatible = "socionext,proxstream2-mioctrl";
+	clock-names = "stdmac";
+	clocks = <&sysctrl 10>;
+};
+
 &peri {
 	compatible = "socionext,proxstream2-perictrl";
 	clock-names = "uart", "fi2c";
-- 
cgit v1.2.1


From 49dde45ba8dd11dfaf157394030cb7e592c01ad9 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:37 +0900
Subject: ARM: dts: uniphier: add clocks properties to EHCI nodes

This allows the EHCI driver to get clocks from device tree.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-ph1-ld4.dtsi  | 3 +++
 arch/arm/dts/uniphier-ph1-pro4.dtsi | 2 ++
 arch/arm/dts/uniphier-ph1-sld3.dtsi | 4 ++++
 arch/arm/dts/uniphier-ph1-sld8.dtsi | 3 +++
 4 files changed, 12 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-ph1-ld4.dtsi b/arch/arm/dts/uniphier-ph1-ld4.dtsi
index 628a397b16..7c8759f929 100644
--- a/arch/arm/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-ld4.dtsi
@@ -115,6 +115,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb0>;
+		clocks = <&mio 3>, <&mio 6>;
 	};
 
 	usb1: usb@5a810100 {
@@ -124,6 +125,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb1>;
+		clocks = <&mio 4>, <&mio 6>;
 	};
 
 	usb2: usb@5a820100 {
@@ -133,6 +135,7 @@
 		interrupts = <0 82 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
+		clocks = <&mio 5>, <&mio 6>;
 	};
 };
 
diff --git a/arch/arm/dts/uniphier-ph1-pro4.dtsi b/arch/arm/dts/uniphier-ph1-pro4.dtsi
index bfffe9464d..cb5b8f1a86 100644
--- a/arch/arm/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/dts/uniphier-ph1-pro4.dtsi
@@ -147,6 +147,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
+		clocks = <&mio 3>, <&mio 6>;
 	};
 
 	usb3: usb@5a810100 {
@@ -156,6 +157,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb3>;
+		clocks = <&mio 4>, <&mio 6>;
 	};
 
 	usb0: usb@65a00000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi
index 91c9ba527f..85dde66f07 100644
--- a/arch/arm/dts/uniphier-ph1-sld3.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi
@@ -191,6 +191,7 @@
 			status = "disabled";
 			reg = <0x5a800100 0x100>;
 			interrupts = <0 80 4>;
+			clocks = <&mio 3>, <&mio 6>;
 		};
 
 		usb1: usb@5a810100 {
@@ -198,6 +199,7 @@
 			status = "disabled";
 			reg = <0x5a810100 0x100>;
 			interrupts = <0 81 4>;
+			clocks = <&mio 4>, <&mio 6>;
 		};
 
 		usb2: usb@5a820100 {
@@ -205,6 +207,7 @@
 			status = "disabled";
 			reg = <0x5a820100 0x100>;
 			interrupts = <0 82 4>;
+			clocks = <&mio 5>, <&mio 6>;
 		};
 
 		usb3: usb@5a830100 {
@@ -212,6 +215,7 @@
 			status = "disabled";
 			reg = <0x5a830100 0x100>;
 			interrupts = <0 83 4>;
+			clocks = <&mio 7>, <&mio 6>;
 		};
 
 		sysctrl: sysctrl@f1840000 {
diff --git a/arch/arm/dts/uniphier-ph1-sld8.dtsi b/arch/arm/dts/uniphier-ph1-sld8.dtsi
index b9ef401885..f93db83661 100644
--- a/arch/arm/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/dts/uniphier-ph1-sld8.dtsi
@@ -115,6 +115,7 @@
 		interrupts = <0 80 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb0>;
+		clocks = <&mio 3>, <&mio 6>;
 	};
 
 	usb1: usb@5a810100 {
@@ -124,6 +125,7 @@
 		interrupts = <0 81 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb1>;
+		clocks = <&mio 4>, <&mio 6>;
 	};
 
 	usb2: usb@5a820100 {
@@ -133,6 +135,7 @@
 		interrupts = <0 82 4>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_usb2>;
+		clocks = <&mio 5>, <&mio 6>;
 	};
 };
 
-- 
cgit v1.2.1


From cd0847fe63e5ec669a497a5cfcb85de33ce6a0d8 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:39 +0900
Subject: ARM: uniphier: switch over to generic EHCI driver

The UniPhier EHCI driver (drivers/usb/host/ehci-uniphier.c) does
nothing special but set the base address and handle reset/clock.

Since commit 4feefdcfe916 ("usb: add clock support for generic EHCI"),
the generic one (drivers/usb/host/ehci-generic.c) can do those, too.

We no longer need to stick to the dedicated driver.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/clk/clk-ph1-ld4.c          | 4 ++--
 arch/arm/mach-uniphier/clk/clk-ph1-pro4.c         | 4 ++--
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c  | 2 +-
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 2 +-
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 2 +-
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
index 4de9bfb102..7a34beea03 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c
@@ -18,7 +18,7 @@ void ph1_ld4_clk_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	tmp |= SC_RSTCTRL_NRST_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
@@ -32,7 +32,7 @@ void ph1_ld4_clk_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_CLKCTRL_CEN_ETHER;
 #endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
index 3df017edd2..c784c314e1 100644
--- a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c
@@ -22,7 +22,7 @@ void ph1_pro4_clk_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_RSTCTRL_NRST_ETHER;
 #endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	tmp |= SC_RSTCTRL_NRST_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
@@ -47,7 +47,7 @@ void ph1_pro4_clk_init(void)
 #ifdef CONFIG_UNIPHIER_ETH
 	tmp |= SC_CLKCTRL_CEN_ETHER;
 #endif
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
 #endif
 #ifdef CONFIG_NAND_DENALI
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
index 8168a63d31..3c06b30a9e 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -35,7 +35,7 @@ void ph1_ld4_pin_init(void)
 	sg_set_pinsel(31, 0, 8, 4);	/* MMCDAT7 -> NFD7_GB */
 #endif
 
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	sg_set_pinsel(53, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
 	sg_set_pinsel(54, 0, 8, 4);	/* USB0OD   -> USB0OD */
 	sg_set_pinsel(55, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
index 23b5f9349a..d5541a9beb 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -40,7 +40,7 @@ void ph1_pro4_pin_init(void)
 	sg_set_pinsel(183, 0, 4, 8);	/* USB1OD   -> USB1OD */
 #endif
 
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	sg_set_pinsel(184, 0, 4, 8);	/* USB2VBUS -> USB2VBUS */
 	sg_set_pinsel(185, 0, 4, 8);	/* USB2OD   -> USB2OD */
 	sg_set_pinsel(187, 0, 4, 8);	/* USB3VBUS -> USB3VBUS */
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
index 6fc0dee70e..367d9f3bbc 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c
@@ -9,7 +9,7 @@
 
 void ph1_sld3_pin_init(void)
 {
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	sg_set_pinsel(13, 0, 4, 4);	/* USB0OC */
 	sg_set_pinsel(14, 1, 4, 4);	/* USB0VBUS */
 
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
index a4e3e7a614..67635844a1 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -33,7 +33,7 @@ void ph1_sld8_pin_init(void)
 	sg_set_pinsel(31, 0, 8, 4);	/* NFD7_GB -> NFD7_GB */
 #endif
 
-#ifdef CONFIG_USB_EHCI_UNIPHIER
+#ifdef CONFIG_USB_EHCI
 	sg_set_pinsel(41, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
 	sg_set_pinsel(42, 0, 8, 4);	/* USB0OD   -> USB0OD */
 	sg_set_pinsel(43, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
-- 
cgit v1.2.1


From 8034b5171fc6c0cfdacf9a4c48bdeb0755a61a3b Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:11:40 +0900
Subject: ARM: uniphier: drop unneeded EHCI pin mux settings

These pin mux settings are cared by the pinctrl drivers.
Remove the ad-hoc code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c  | 9 ---------
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 7 -------
 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 9 ---------
 3 files changed, 25 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
index 3c06b30a9e..2fe2c7fc80 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c
@@ -35,15 +35,6 @@ void ph1_ld4_pin_init(void)
 	sg_set_pinsel(31, 0, 8, 4);	/* MMCDAT7 -> NFD7_GB */
 #endif
 
-#ifdef CONFIG_USB_EHCI
-	sg_set_pinsel(53, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
-	sg_set_pinsel(54, 0, 8, 4);	/* USB0OD   -> USB0OD */
-	sg_set_pinsel(55, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
-	sg_set_pinsel(56, 0, 8, 4);	/* USB1OD   -> USB1OD */
-	/* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */
-	/* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */
-#endif
-
 	tmp = readl(SG_IECTRL);
 	tmp |= 0x41;
 	writel(tmp, SG_IECTRL);
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
index d5541a9beb..b08ca1ef31 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c
@@ -40,12 +40,5 @@ void ph1_pro4_pin_init(void)
 	sg_set_pinsel(183, 0, 4, 8);	/* USB1OD   -> USB1OD */
 #endif
 
-#ifdef CONFIG_USB_EHCI
-	sg_set_pinsel(184, 0, 4, 8);	/* USB2VBUS -> USB2VBUS */
-	sg_set_pinsel(185, 0, 4, 8);	/* USB2OD   -> USB2OD */
-	sg_set_pinsel(187, 0, 4, 8);	/* USB3VBUS -> USB3VBUS */
-	sg_set_pinsel(188, 0, 4, 8);	/* USB3OD   -> USB3OD */
-#endif
-
 	writel(1, SG_LOADPINCTRL);
 }
diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
index 67635844a1..f3fae1d7c6 100644
--- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
+++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c
@@ -32,13 +32,4 @@ void ph1_sld8_pin_init(void)
 	sg_set_pinsel(30, 0, 8, 4);	/* NFD6_GB -> NFD6_GB */
 	sg_set_pinsel(31, 0, 8, 4);	/* NFD7_GB -> NFD7_GB */
 #endif
-
-#ifdef CONFIG_USB_EHCI
-	sg_set_pinsel(41, 0, 8, 4);	/* USB0VBUS -> USB0VBUS */
-	sg_set_pinsel(42, 0, 8, 4);	/* USB0OD   -> USB0OD */
-	sg_set_pinsel(43, 0, 8, 4);	/* USB1VBUS -> USB1VBUS */
-	sg_set_pinsel(44, 0, 8, 4);	/* USB1OD   -> USB1OD */
-	/* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */
-	/* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */
-#endif
 }
-- 
cgit v1.2.1


From 2851971b8ffd0508323dbd661138b6fa533b1c07 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Tue, 2 Feb 2016 21:51:41 +0900
Subject: ARM: uniphier: remove unused header mio-regs.h

This header is no longer used.

This is the last file in arch/arm/mach-uniphier/include/mach/.
At last, I've succeeded in eliminating the mach directory.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/include/mach/mio-regs.h | 20 --------------------
 1 file changed, 20 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/include/mach/mio-regs.h

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/include/mach/mio-regs.h b/arch/arm/mach-uniphier/include/mach/mio-regs.h
deleted file mode 100644
index 3306934ff7..0000000000
--- a/arch/arm/mach-uniphier/include/mach/mio-regs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * UniPhier MIO (Media I/O) registers
- *
- * Copyright (C) 2014 Panasonic Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef ARCH_MIO_REGS_H
-#define ARCH_MIO_REGS_H
-
-#define MIO_BASE		0x59810000
-
-#define MIO_CLKCTRL(i)		(MIO_BASE + 0x200 * (i) + 0x0020)
-#define MIO_RSTCTRL(i)		(MIO_BASE + 0x200 * (i) + 0x0110)
-#define MIO_USB_RSTCTRL(i)	(MIO_BASE + 0x200 * (i) + 0x0114)
-
-#define MIO_USB_RSTCTRL_XRST	(0x1 << 0)
-
-#endif /* ARCH_MIO_REGS_H */
-- 
cgit v1.2.1


From 126f9bad77ad6f373de857eb88d0d9f284ee2709 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 5 Feb 2016 13:20:31 +0900
Subject: ARM: uniphier: fix makefiles to build cmd_ddr(m)phy.c

The U-Boot proper building needs to descend arch/arm/mach-uniphier/dram
to build these commands.

Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/Makefile      | 3 ++-
 arch/arm/mach-uniphier/dram/Makefile | 6 ++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile
index 491e78e415..e65d602350 100644
--- a/arch/arm/mach-uniphier/Makefile
+++ b/arch/arm/mach-uniphier/Makefile
@@ -6,7 +6,7 @@ ifdef CONFIG_SPL_BUILD
 
 obj-y += lowlevel_init.o
 
-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ dram/
+obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/
 
 obj-$(CONFIG_DEBUG_LL) += debug_ll.o
@@ -32,5 +32,6 @@ obj-y += timer.o
 obj-y += boards.o
 obj-y += soc_info.o
 obj-y += boot-mode/
+obj-y += dram/
 
 obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index cab7df1653..a0a6003065 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -2,6 +2,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+ifdef CONFIG_SPL_BUILD
+
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4)	+= umc-ph1-ld4.o \
 					   ddrphy-training.o ddrphy-ph1-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4)	+= umc-ph1-pro4.o \
@@ -11,5 +13,9 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8)	+= umc-ph1-sld8.o \
 obj-$(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)	+= umc-proxstream2.o
 obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD6B)	+= umc-proxstream2.o
 
+else
+
 obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o
 obj-$(CONFIG_CMD_DDRMPHY_DUMP) += cmd_ddrmphy.o
+
+endif
-- 
cgit v1.2.1


From c9552895a8055fed424d6817008fccd37dbfd01c Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 5 Feb 2016 13:20:32 +0900
Subject: ARM: uniphier: move cmd_ddrmphy.c to fix build error

If CONFIG_CMD_DDRMPHY_DUMP is enabled, the build fails.

Fixes: 93d92d46cd01 ("ARM: uniphier: add dump command for DDR Multi PHY registers")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/cmd_ddrmphy.c      | 329 ------------------------------
 arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 329 ++++++++++++++++++++++++++++++
 2 files changed, 329 insertions(+), 329 deletions(-)
 delete mode 100644 arch/arm/mach-uniphier/cmd_ddrmphy.c
 create mode 100644 arch/arm/mach-uniphier/dram/cmd_ddrmphy.c

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/cmd_ddrmphy.c b/arch/arm/mach-uniphier/cmd_ddrmphy.c
deleted file mode 100644
index c18f099f2c..0000000000
--- a/arch/arm/mach-uniphier/cmd_ddrmphy.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/io.h>
-
-#include "../init.h"
-#include "ddrmphy-regs.h"
-
-/* Select either decimal or hexadecimal */
-#if 1
-#define PRINTF_FORMAT "%2d"
-#else
-#define PRINTF_FORMAT "%02x"
-#endif
-/* field separator */
-#define FS "   "
-
-static void __iomem *get_phy_base(int ch)
-{
-	return (void __iomem *)(0x5b830000 + ch * 0x00200000);
-}
-
-static int get_nr_ch(void)
-{
-	const struct uniphier_board_data *bd = uniphier_get_board_param();
-
-	return bd->dram_ch2_width ? 3 : 2;
-}
-
-static int get_nr_datx8(int ch)
-{
-	unsigned int width;
-
-	const struct uniphier_board_data *bd = uniphier_get_board_param();
-
-	switch (ch) {
-	case 0:
-		width = bd->dram_ch0_width;
-		break;
-	case 1:
-		width = bd->dram_ch1_width;
-		break;
-	default:
-		width = bd->dram_ch2_width;
-		break;
-	}
-
-	return width / 8;
-}
-
-static void print_bdl(void __iomem *reg, int n)
-{
-	u32 val = readl(reg);
-	int i;
-
-	for (i = 0; i < n; i++)
-		printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
-}
-
-static void dump_loop(void (*callback)(void __iomem *))
-{
-	int ch, dx, nr_ch, nr_dx;
-	void __iomem *dx_base;
-
-	nr_ch = get_nr_ch();
-
-	for (ch = 0; ch < nr_ch; ch++) {
-		dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
-		nr_dx = get_nr_datx8(ch);
-
-		for (dx = 0; dx < nr_dx; dx++) {
-			printf("CH%dDX%d:", ch, dx);
-			(*callback)(dx_base);
-			dx_base += DMPHY_DX_STRIDE;
-			printf("\n");
-		}
-	}
-}
-
-static void zq_dump(void)
-{
-	int ch, zq, nr_ch, nr_zq, i;
-	void __iomem *zq_base;
-	u32 dr, pr;
-
-	printf("\n--- Impedance Data ---\n");
-	printf("         ZPD  ZPU  OPD  OPU  ZDV  ODV\n");
-
-	nr_ch = get_nr_ch();
-
-	for (ch = 0; ch < nr_ch; ch++) {
-		zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
-		nr_zq = 3;
-
-		for (zq = 0; zq < nr_zq; zq++) {
-			printf("CH%dZQ%d:", ch, zq);
-
-			dr = readl(zq_base + DMPHY_ZQ_DR);
-			for (i = 0; i < 4; i++) {
-				printf(FS PRINTF_FORMAT, dr & 0x7f);
-				dr >>= 7;
-			}
-
-			pr = readl(zq_base + DMPHY_ZQ_PR);
-			for (i = 0; i < 2; i++) {
-				printf(FS PRINTF_FORMAT, pr & 0xf);
-				pr >>= 4;
-			}
-
-			zq_base += DMPHY_ZQ_STRIDE;
-			printf("\n");
-		}
-	}
-}
-
-static void __wbdl_dump(void __iomem *dx_base)
-{
-	print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
-	print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
-	print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
-
-	printf(FS "(+" PRINTF_FORMAT ")",
-	       readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
-}
-
-static void wbdl_dump(void)
-{
-	printf("\n--- Write Bit Delay Line ---\n");
-	printf("         DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
-
-	dump_loop(&__wbdl_dump);
-}
-
-static void __rbdl_dump(void __iomem *dx_base)
-{
-	print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
-	print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
-	print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
-
-	printf(FS "(+" PRINTF_FORMAT ")",
-	       (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
-
-	printf(FS "(+" PRINTF_FORMAT ")",
-	       (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
-}
-
-static void rbdl_dump(void)
-{
-	printf("\n--- Read Bit Delay Line ---\n");
-	printf("         DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD) (RDQSND)\n");
-
-	dump_loop(&__rbdl_dump);
-}
-
-static void __wld_dump(void __iomem *dx_base)
-{
-	int rank;
-	u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
-	u32 gtr = readl(dx_base + DMPHY_DX_GTR);
-
-	for (rank = 0; rank < 4; rank++) {
-		u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
-		u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
-
-		printf(FS PRINTF_FORMAT "%sT", wld,
-		       wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
-	}
-}
-
-static void wld_dump(void)
-{
-	printf("\n--- Write Leveling Delay ---\n");
-	printf("          Rank0   Rank1   Rank2   Rank3\n");
-
-	dump_loop(&__wld_dump);
-}
-
-static void __dqsgd_dump(void __iomem *dx_base)
-{
-	int rank;
-	u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
-	u32 gtr = readl(dx_base + DMPHY_DX_GTR);
-
-	for (rank = 0; rank < 4; rank++) {
-		u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
-		u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
-
-		printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
-	}
-}
-
-static void dqsgd_dump(void)
-{
-	printf("\n--- DQS Gating Delay ---\n");
-	printf("          Rank0   Rank1   Rank2   Rank3\n");
-
-	dump_loop(&__dqsgd_dump);
-}
-
-static void __mdl_dump(void __iomem *dx_base)
-{
-	int i;
-	u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
-
-	for (i = 0; i < 3; i++)
-		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
-}
-
-static void mdl_dump(void)
-{
-	printf("\n--- Master Delay Line ---\n");
-	printf("        IPRD TPRD MDLD\n");
-
-	dump_loop(&__mdl_dump);
-}
-
-#define REG_DUMP(x)							\
-	{ int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst;	\
-		printf("%3d: %-10s: %p : %08x\n",			\
-		       ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
-
-#define DX_REG_DUMP(dx, x)						\
-	{ int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) +		\
-			DMPHY_DX_## x;					\
-		void __iomem *reg = phy_base + ofst;			\
-		printf("%3d: DX%d%-7s: %p : %08x\n",			\
-		       ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
-
-static void reg_dump(void)
-{
-	int ch, dx, nr_ch, nr_dx;
-	void __iomem *phy_base;
-
-	printf("\n--- DDR PHY registers ---\n");
-
-	nr_ch = get_nr_ch();
-
-	for (ch = 0; ch < nr_ch; ch++) {
-		phy_base = get_phy_base(ch);
-		nr_dx = get_nr_datx8(ch);
-
-		printf("== Ch%d ==\n", ch);
-		printf(" No: Name      : Address  : Data\n");
-
-		REG_DUMP(RIDR);
-		REG_DUMP(PIR);
-		REG_DUMP(PGCR0);
-		REG_DUMP(PGCR1);
-		REG_DUMP(PGCR2);
-		REG_DUMP(PGCR3);
-		REG_DUMP(PGSR0);
-		REG_DUMP(PGSR1);
-		REG_DUMP(PLLCR);
-		REG_DUMP(PTR0);
-		REG_DUMP(PTR1);
-		REG_DUMP(PTR2);
-		REG_DUMP(PTR3);
-		REG_DUMP(PTR4);
-		REG_DUMP(ACMDLR);
-		REG_DUMP(ACBDLR0);
-		REG_DUMP(DXCCR);
-		REG_DUMP(DSGCR);
-		REG_DUMP(DCR);
-		REG_DUMP(DTPR0);
-		REG_DUMP(DTPR1);
-		REG_DUMP(DTPR2);
-		REG_DUMP(DTPR3);
-		REG_DUMP(MR0);
-		REG_DUMP(MR1);
-		REG_DUMP(MR2);
-		REG_DUMP(MR3);
-
-		for (dx = 0; dx < nr_dx; dx++) {
-			DX_REG_DUMP(dx, GCR0);
-			DX_REG_DUMP(dx, GCR1);
-			DX_REG_DUMP(dx, GCR2);
-			DX_REG_DUMP(dx, GCR3);
-			DX_REG_DUMP(dx, GTR);
-		}
-	}
-}
-
-static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	char *cmd = argv[1];
-
-	if (argc == 1)
-		cmd = "all";
-
-	if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
-		zq_dump();
-
-	if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
-		wbdl_dump();
-
-	if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
-		rbdl_dump();
-
-	if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
-		wld_dump();
-
-	if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
-		dqsgd_dump();
-
-	if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
-		mdl_dump();
-
-	if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
-		reg_dump();
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	ddrm,	2,	1,	do_ddrm,
-	"UniPhier DDR PHY parameters dumper",
-	"- dump all of the followings\n"
-	"ddrm zq - dump Impedance Data\n"
-	"ddrm wbdl - dump Write Bit Delay\n"
-	"ddrm rbdl - dump Read Bit Delay\n"
-	"ddrm wld - dump Write Leveling\n"
-	"ddrm dqsgd - dump DQS Gating Delay\n"
-	"ddrm mdl - dump Master Delay Line\n"
-	"ddrm reg - dump registers\n"
-);
diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
new file mode 100644
index 0000000000..c18f099f2c
--- /dev/null
+++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/io.h>
+
+#include "../init.h"
+#include "ddrmphy-regs.h"
+
+/* Select either decimal or hexadecimal */
+#if 1
+#define PRINTF_FORMAT "%2d"
+#else
+#define PRINTF_FORMAT "%02x"
+#endif
+/* field separator */
+#define FS "   "
+
+static void __iomem *get_phy_base(int ch)
+{
+	return (void __iomem *)(0x5b830000 + ch * 0x00200000);
+}
+
+static int get_nr_ch(void)
+{
+	const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+	return bd->dram_ch2_width ? 3 : 2;
+}
+
+static int get_nr_datx8(int ch)
+{
+	unsigned int width;
+
+	const struct uniphier_board_data *bd = uniphier_get_board_param();
+
+	switch (ch) {
+	case 0:
+		width = bd->dram_ch0_width;
+		break;
+	case 1:
+		width = bd->dram_ch1_width;
+		break;
+	default:
+		width = bd->dram_ch2_width;
+		break;
+	}
+
+	return width / 8;
+}
+
+static void print_bdl(void __iomem *reg, int n)
+{
+	u32 val = readl(reg);
+	int i;
+
+	for (i = 0; i < n; i++)
+		printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
+}
+
+static void dump_loop(void (*callback)(void __iomem *))
+{
+	int ch, dx, nr_ch, nr_dx;
+	void __iomem *dx_base;
+
+	nr_ch = get_nr_ch();
+
+	for (ch = 0; ch < nr_ch; ch++) {
+		dx_base = get_phy_base(ch) + DMPHY_DX_BASE;
+		nr_dx = get_nr_datx8(ch);
+
+		for (dx = 0; dx < nr_dx; dx++) {
+			printf("CH%dDX%d:", ch, dx);
+			(*callback)(dx_base);
+			dx_base += DMPHY_DX_STRIDE;
+			printf("\n");
+		}
+	}
+}
+
+static void zq_dump(void)
+{
+	int ch, zq, nr_ch, nr_zq, i;
+	void __iomem *zq_base;
+	u32 dr, pr;
+
+	printf("\n--- Impedance Data ---\n");
+	printf("         ZPD  ZPU  OPD  OPU  ZDV  ODV\n");
+
+	nr_ch = get_nr_ch();
+
+	for (ch = 0; ch < nr_ch; ch++) {
+		zq_base = get_phy_base(ch) + DMPHY_ZQ_BASE;
+		nr_zq = 3;
+
+		for (zq = 0; zq < nr_zq; zq++) {
+			printf("CH%dZQ%d:", ch, zq);
+
+			dr = readl(zq_base + DMPHY_ZQ_DR);
+			for (i = 0; i < 4; i++) {
+				printf(FS PRINTF_FORMAT, dr & 0x7f);
+				dr >>= 7;
+			}
+
+			pr = readl(zq_base + DMPHY_ZQ_PR);
+			for (i = 0; i < 2; i++) {
+				printf(FS PRINTF_FORMAT, pr & 0xf);
+				pr >>= 4;
+			}
+
+			zq_base += DMPHY_ZQ_STRIDE;
+			printf("\n");
+		}
+	}
+}
+
+static void __wbdl_dump(void __iomem *dx_base)
+{
+	print_bdl(dx_base + DMPHY_DX_BDLR0, 4);
+	print_bdl(dx_base + DMPHY_DX_BDLR1, 4);
+	print_bdl(dx_base + DMPHY_DX_BDLR2, 2);
+
+	printf(FS "(+" PRINTF_FORMAT ")",
+	       readl(dx_base + DMPHY_DX_LCDLR1) & 0xff);
+}
+
+static void wbdl_dump(void)
+{
+	printf("\n--- Write Bit Delay Line ---\n");
+	printf("         DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");
+
+	dump_loop(&__wbdl_dump);
+}
+
+static void __rbdl_dump(void __iomem *dx_base)
+{
+	print_bdl(dx_base + DMPHY_DX_BDLR3, 4);
+	print_bdl(dx_base + DMPHY_DX_BDLR4, 4);
+	print_bdl(dx_base + DMPHY_DX_BDLR5, 1);
+
+	printf(FS "(+" PRINTF_FORMAT ")",
+	       (readl(dx_base + DMPHY_DX_LCDLR1) >> 8) & 0xff);
+
+	printf(FS "(+" PRINTF_FORMAT ")",
+	       (readl(dx_base + DMPHY_DX_LCDLR1) >> 16) & 0xff);
+}
+
+static void rbdl_dump(void)
+{
+	printf("\n--- Read Bit Delay Line ---\n");
+	printf("         DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD) (RDQSND)\n");
+
+	dump_loop(&__rbdl_dump);
+}
+
+static void __wld_dump(void __iomem *dx_base)
+{
+	int rank;
+	u32 lcdlr0 = readl(dx_base + DMPHY_DX_LCDLR0);
+	u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+	for (rank = 0; rank < 4; rank++) {
+		u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
+		u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
+
+		printf(FS PRINTF_FORMAT "%sT", wld,
+		       wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
+	}
+}
+
+static void wld_dump(void)
+{
+	printf("\n--- Write Leveling Delay ---\n");
+	printf("          Rank0   Rank1   Rank2   Rank3\n");
+
+	dump_loop(&__wld_dump);
+}
+
+static void __dqsgd_dump(void __iomem *dx_base)
+{
+	int rank;
+	u32 lcdlr2 = readl(dx_base + DMPHY_DX_LCDLR2);
+	u32 gtr = readl(dx_base + DMPHY_DX_GTR);
+
+	for (rank = 0; rank < 4; rank++) {
+		u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
+		u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
+
+		printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
+	}
+}
+
+static void dqsgd_dump(void)
+{
+	printf("\n--- DQS Gating Delay ---\n");
+	printf("          Rank0   Rank1   Rank2   Rank3\n");
+
+	dump_loop(&__dqsgd_dump);
+}
+
+static void __mdl_dump(void __iomem *dx_base)
+{
+	int i;
+	u32 mdl = readl(dx_base + DMPHY_DX_MDLR);
+
+	for (i = 0; i < 3; i++)
+		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
+}
+
+static void mdl_dump(void)
+{
+	printf("\n--- Master Delay Line ---\n");
+	printf("        IPRD TPRD MDLD\n");
+
+	dump_loop(&__mdl_dump);
+}
+
+#define REG_DUMP(x)							\
+	{ int ofst = DMPHY_ ## x; void __iomem *reg = phy_base + ofst;	\
+		printf("%3d: %-10s: %p : %08x\n",			\
+		       ofst >> DMPHY_SHIFT, #x, reg, readl(reg)); }
+
+#define DX_REG_DUMP(dx, x)						\
+	{ int ofst = DMPHY_DX_BASE + DMPHY_DX_STRIDE * (dx) +		\
+			DMPHY_DX_## x;					\
+		void __iomem *reg = phy_base + ofst;			\
+		printf("%3d: DX%d%-7s: %p : %08x\n",			\
+		       ofst >> DMPHY_SHIFT, (dx), #x, reg, readl(reg)); }
+
+static void reg_dump(void)
+{
+	int ch, dx, nr_ch, nr_dx;
+	void __iomem *phy_base;
+
+	printf("\n--- DDR PHY registers ---\n");
+
+	nr_ch = get_nr_ch();
+
+	for (ch = 0; ch < nr_ch; ch++) {
+		phy_base = get_phy_base(ch);
+		nr_dx = get_nr_datx8(ch);
+
+		printf("== Ch%d ==\n", ch);
+		printf(" No: Name      : Address  : Data\n");
+
+		REG_DUMP(RIDR);
+		REG_DUMP(PIR);
+		REG_DUMP(PGCR0);
+		REG_DUMP(PGCR1);
+		REG_DUMP(PGCR2);
+		REG_DUMP(PGCR3);
+		REG_DUMP(PGSR0);
+		REG_DUMP(PGSR1);
+		REG_DUMP(PLLCR);
+		REG_DUMP(PTR0);
+		REG_DUMP(PTR1);
+		REG_DUMP(PTR2);
+		REG_DUMP(PTR3);
+		REG_DUMP(PTR4);
+		REG_DUMP(ACMDLR);
+		REG_DUMP(ACBDLR0);
+		REG_DUMP(DXCCR);
+		REG_DUMP(DSGCR);
+		REG_DUMP(DCR);
+		REG_DUMP(DTPR0);
+		REG_DUMP(DTPR1);
+		REG_DUMP(DTPR2);
+		REG_DUMP(DTPR3);
+		REG_DUMP(MR0);
+		REG_DUMP(MR1);
+		REG_DUMP(MR2);
+		REG_DUMP(MR3);
+
+		for (dx = 0; dx < nr_dx; dx++) {
+			DX_REG_DUMP(dx, GCR0);
+			DX_REG_DUMP(dx, GCR1);
+			DX_REG_DUMP(dx, GCR2);
+			DX_REG_DUMP(dx, GCR3);
+			DX_REG_DUMP(dx, GTR);
+		}
+	}
+}
+
+static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	char *cmd = argv[1];
+
+	if (argc == 1)
+		cmd = "all";
+
+	if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
+		zq_dump();
+
+	if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
+		wbdl_dump();
+
+	if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
+		rbdl_dump();
+
+	if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
+		wld_dump();
+
+	if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
+		dqsgd_dump();
+
+	if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
+		mdl_dump();
+
+	if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
+		reg_dump();
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	ddrm,	2,	1,	do_ddrm,
+	"UniPhier DDR PHY parameters dumper",
+	"- dump all of the followings\n"
+	"ddrm zq - dump Impedance Data\n"
+	"ddrm wbdl - dump Write Bit Delay\n"
+	"ddrm rbdl - dump Read Bit Delay\n"
+	"ddrm wld - dump Write Leveling\n"
+	"ddrm dqsgd - dump DQS Gating Delay\n"
+	"ddrm mdl - dump Master Delay Line\n"
+	"ddrm reg - dump registers\n"
+);
-- 
cgit v1.2.1


From f775c09d00cc355a87cf4ba935eff86eacd0c961 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 5 Feb 2016 13:21:07 +0900
Subject: ARM: uniphier: adjust DDR clock delay line for ProXstream2

It turned out that DDR channel 2 was not working on ProXstream2
Vodka board.  Add the missing ACBLDR0 register setting to adjust
the delay between the clock lines and the address/command lines.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/mach-uniphier/dram/umc-proxstream2.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

(limited to 'arch')

diff --git a/arch/arm/mach-uniphier/dram/umc-proxstream2.c b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
index bb7acdee1e..6e7fa885c4 100644
--- a/arch/arm/mach-uniphier/dram/umc-proxstream2.c
+++ b/arch/arm/mach-uniphier/dram/umc-proxstream2.c
@@ -18,6 +18,8 @@
 #include "ddrmphy-regs.h"
 #include "umc-regs.h"
 
+#define CH_NR	3
+
 enum dram_freq {
 	FREQ_1866M,
 	FREQ_2133M,
@@ -43,6 +45,9 @@ static u32 ddrphy_dtpr3[FREQ_NR] = {0x0010cb49, 0x0010ec89};
 static u32 ddrphy_mr0[FREQ_NR] = {0x00000115, 0x00000125};
 static u32 ddrphy_mr2[FREQ_NR] = {0x000002a0, 0x000002a8};
 
+/* dependent on package and board design */
+static u32 ddrphy_acbdlr0[CH_NR] = {0x0000000c, 0x0000000c, 0x00000009};
+
 static u32 umc_cmdctla[FREQ_NR] = {0x66DD131D, 0x77EE1722};
 /*
  * The ch2 is a different generation UMC core.
@@ -150,7 +155,8 @@ static int ddrphy_get_system_latency(void __iomem *phy_base, int width)
 	return dgsl_max;
 }
 
-static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
+static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width,
+			int ch)
 {
 	u32 tmp;
 	void __iomem *zq_base, *dx_base;
@@ -178,6 +184,8 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq, int width)
 	writel(ddrphy_ptr3[freq],  phy_base + DMPHY_PTR3);
 	writel(ddrphy_ptr4[freq],  phy_base + DMPHY_PTR4);
 
+	writel(ddrphy_acbdlr0[ch], phy_base + DMPHY_ACBDLR0);
+
 	writel(0x55555555, phy_base + DMPHY_ACIOCR1);
 	writel(0x00000000, phy_base + DMPHY_ACIOCR2);
 	writel(0x55555555, phy_base + DMPHY_ACIOCR3);
@@ -528,7 +536,7 @@ static int umc_init(void __iomem *umc_base, enum dram_freq freq, int ch,
 	writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
 	       umc_dc_base + UMC_DIOCTLA);
 
-	ddrphy_init(phy_base, freq, width);
+	ddrphy_init(phy_base, freq, width, ch);
 
 	ret = ddrphy_impedance_calibration(phy_base);
 	if (ret)
-- 
cgit v1.2.1


From a65256d304a28b05426ac361629a44b6f8c3073d Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 12 Feb 2016 20:27:00 +0900
Subject: ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board

This board has an EEPROM connected to the I2C channel 0 of the SoC.
Its slave address is 0x54.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-proxstream2-gentil.dts | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index c6c133aa19..fb79555ef6 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -39,6 +39,12 @@
 
 &i2c0 {
 	status = "okay";
+
+	eeprom {
+		compatible = "24c64", "i2c-eeprom";
+		reg = <0x54>;
+		u-boot,i2c-offset-len = <2>;
+	};
 };
 
 &usb0 {
-- 
cgit v1.2.1


From 500aacabef1744b87001cf690896d694796bdab9 Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 12 Feb 2016 20:27:01 +0900
Subject: ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board

This is used for on-board inter-connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/uniphier-proxstream2-gentil.dts | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'arch')

diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts
index fb79555ef6..dc0def30fd 100644
--- a/arch/arm/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts
@@ -27,6 +27,7 @@
 		serial1 = &serial1;
 		serial2 = &serial2;
 		i2c0 = &i2c0;
+		i2c2 = &i2c2;
 		i2c4 = &i2c4;
 		i2c5 = &i2c5;
 		i2c6 = &i2c6;
@@ -47,6 +48,10 @@
 	};
 };
 
+&i2c2 {
+	status = "okay";
+};
+
 &usb0 {
 	status = "okay";
 };
-- 
cgit v1.2.1


From 3f23111722ebf5b2416c7989eab7eb77be5ad0cf Mon Sep 17 00:00:00 2001
From: Masahiro Yamada <yamada.masahiro@socionext.com>
Date: Fri, 12 Feb 2016 20:27:02 +0900
Subject: ARM: uniphier: add support for PH1-Pro4 Ace and Sanji boards

Initial commit for PH1-Pro4 Ace and Sanji boards.

Note:
There are two variants for the Ace board in terms of the amount of
DDR memory; 1GB or 2GB.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
 arch/arm/dts/Makefile                    |   2 +
 arch/arm/dts/uniphier-ph1-pro4-ace.dts   | 105 +++++++++++++++++++++++++++++++
 arch/arm/dts/uniphier-ph1-pro4-sanji.dts | 100 +++++++++++++++++++++++++++++
 arch/arm/mach-uniphier/board_late_init.c |   2 +
 arch/arm/mach-uniphier/boards.c          |  14 +++++
 5 files changed, 223 insertions(+)
 create mode 100644 arch/arm/dts/uniphier-ph1-pro4-ace.dts
 create mode 100644 arch/arm/dts/uniphier-ph1-pro4-sanji.dts

(limited to 'arch')

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0fa5796946..b574284262 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -59,7 +59,9 @@ dtb-$(CONFIG_ARCH_MVEBU) +=			\
 dtb-$(CONFIG_ARCH_UNIPHIER) += \
 	uniphier-ph1-ld4-ref.dtb \
 	uniphier-ph1-ld6b-ref.dtb \
+	uniphier-ph1-pro4-ace.dtb \
 	uniphier-ph1-pro4-ref.dtb \
+	uniphier-ph1-pro4-sanji.dtb \
 	uniphier-ph1-pro5-4kbox.dtb \
 	uniphier-ph1-sld3-ref.dtb \
 	uniphier-ph1-sld8-ref.dtb \
diff --git a/arch/arm/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/dts/uniphier-ph1-pro4-ace.dts
new file mode 100644
index 0000000000..6e741ea45b
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4-ace.dts
@@ -0,0 +1,105 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Ace Board
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+	X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+	model = "UniPhier PH1-Pro4 Ace Board";
+	compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x40000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		serial2 = &serial2;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&serial2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom {
+		compatible = "24c64", "i2c-eeprom";
+		reg = <0x54>;
+		u-boot,i2c-offset-len = <2>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+/* for U-Boot only */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
new file mode 100644
index 0000000000..91a71ef469
--- /dev/null
+++ b/arch/arm/dts/uniphier-ph1-pro4-sanji.dts
@@ -0,0 +1,100 @@
+/*
+ * Device Tree Source for UniPhier PH1-Pro4 Sanji Board
+ *
+ * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+	X11
+ */
+
+/dts-v1/;
+/include/ "uniphier-ph1-pro4.dtsi"
+
+/ {
+	model = "UniPhier PH1-Pro4 Sanji Board";
+	compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4";
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &serial0;
+		serial1 = &serial1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+	};
+};
+
+&serial0 {
+	status = "okay";
+};
+
+&serial1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	eeprom {
+		compatible = "24c64", "i2c-eeprom";
+		reg = <0x54>;
+		u-boot,i2c-offset-len = <2>;
+	};
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&i2c2 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+};
+
+&usb0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&usb2 {
+	status = "okay";
+};
+
+&usb3 {
+	status = "okay";
+};
+
+/* for U-Boot only */
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&serial0 {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl {
+	u-boot,dm-pre-reloc;
+};
+
+&pinctrl_uart0 {
+	u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c
index eba48a248d..6e2008ccd7 100644
--- a/arch/arm/mach-uniphier/board_late_init.c
+++ b/arch/arm/mach-uniphier/board_late_init.c
@@ -37,7 +37,9 @@ static const struct uniphier_fdt_file uniphier_fdt_files[] = {
 	{ "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", },
 	{ "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", },
 	{ "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", },
+	{ "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", },
 	{ "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", },
+	{ "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", },
 	{ "socionext,ph1-pro5-4kbox", "uniphier-ph1-pro5-4kbox.dtb", },
 	{ "socionext,ph1-sld3-ref", "uniphier-ph1-sld3-ref.dtb", },
 	{ "socionext,ph1-sld8-ref", "uniphier-ph1-sld8-ref.dtb", },
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index f12415022b..d70c712206 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -40,6 +40,7 @@ static const struct uniphier_board_data ph1_ld4_data = {
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+/* 1GB RAM board */
 static const struct uniphier_board_data ph1_pro4_data = {
 	.dram_ch0_base	= 0x80000000,
 	.dram_ch0_size	= 0x20000000,
@@ -49,6 +50,17 @@ static const struct uniphier_board_data ph1_pro4_data = {
 	.dram_ch1_width	= 32,
 	.dram_freq	= 1600,
 };
+
+/* 2GB RAM board */
+static const struct uniphier_board_data ph1_pro4_2g_data = {
+	.dram_ch0_base	= 0x80000000,
+	.dram_ch0_size	= 0x40000000,
+	.dram_ch0_width	= 32,
+	.dram_ch1_base	= 0xc0000000,
+	.dram_ch1_size	= 0x40000000,
+	.dram_ch1_width	= 32,
+	.dram_freq	= 1600,
+};
 #endif
 
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
@@ -118,6 +130,8 @@ static const struct uniphier_board_id uniphier_boards[] = {
 	{ "socionext,ph1-ld4", &ph1_ld4_data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
+	{ "socionext,ph1-pro4-ace", &ph1_pro4_2g_data, },
+	{ "socionext,ph1-pro4-sanji", &ph1_pro4_2g_data, },
 	{ "socionext,ph1-pro4", &ph1_pro4_data, },
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
-- 
cgit v1.2.1