From 137703b811502dfea364650fb3e17f20b4c21333 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20M=C3=BCller?= Date: Wed, 4 Jan 2012 15:26:25 +0000 Subject: overo: add SPL support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard * run-tested with x-loader Signed-off-by: Andreas Müller Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap3/mem.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch') diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 5fd02d4dfc..4ca929edea 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -123,6 +123,32 @@ enum { V_MCFG_BANKALLOCATION_RBC | \ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR +/* Hynix part of Overo (165MHz optimized) 6.06ns */ +#define HYNIX_TDAL_165 6 +#define HYNIX_TDPL_165 3 +#define HYNIX_TRRD_165 2 +#define HYNIX_TRCD_165 3 +#define HYNIX_TRP_165 3 +#define HYNIX_TRAS_165 7 +#define HYNIX_TRC_165 10 +#define HYNIX_TRFC_165 21 +#define HYNIX_V_ACTIMA_165 \ + ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ + HYNIX_TRAS_165, HYNIX_TRP_165, \ + HYNIX_TRCD_165, HYNIX_TRRD_165, \ + HYNIX_TDPL_165, HYNIX_TDAL_165) + +#define HYNIX_TWTR_165 1 +#define HYNIX_TCKE_165 1 +#define HYNIX_TXP_165 2 +#define HYNIX_XSR_165 24 +#define HYNIX_V_ACTIMB_165 \ + ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ + HYNIX_TXP_165, HYNIX_XSR_165) + +#define HYNIX_RASWIDTH_165 0x2 +#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) + /* Hynix part of AM/DM37xEVM (200MHz optimized) */ #define HYNIX_TDAL_200 6 #define HYNIX_TDPL_200 3 -- cgit v1.2.1