From 638a05894169b07ea8f6d21b6925ca353ea6ebb7 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 11 Oct 2015 21:37:44 -0700 Subject: x86: Enable mrc cache for bayleybay and minnowmax Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/bayleybay.dts | 6 ++++++ arch/x86/dts/minnowmax.dts | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'arch/x86') diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index d646987ff8..52d0999f19 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -68,9 +68,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "winbond,w25q64dw", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006e0000 0x00010000>; + }; }; }; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index e917f0f55b..b03f9878dd 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -273,9 +273,15 @@ #size-cells = <0>; compatible = "intel,ich-spi"; spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; reg = <0>; compatible = "stmicro,n25q064a", "spi-flash"; memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; }; }; -- cgit v1.2.1