From cdb6babec6422ad4b89e447b1b468f625deaea79 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Tue, 23 Jun 2015 12:18:55 +0800 Subject: x86: queensbay: Change PCIe root ports' interrupt routing So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/dts/crownbay.dts | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) (limited to 'arch/x86/dts') diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index b77c65a463..60da1f544b 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -169,10 +169,22 @@ /* TunnelCreek PCI devices */ PCI_BDF(0, 2, 0) INTA PIRQE PCI_BDF(0, 3, 0) INTA PIRQF - PCI_BDF(0, 23, 0) INTA PIRQE - PCI_BDF(0, 24, 0) INTA PIRQF - PCI_BDF(0, 25, 0) INTA PIRQG - PCI_BDF(0, 26, 0) INTA PIRQH + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTB PIRQB + PCI_BDF(0, 23, 0) INTC PIRQC + PCI_BDF(0, 23, 0) INTD PIRQD + PCI_BDF(0, 24, 0) INTA PIRQB + PCI_BDF(0, 24, 0) INTB PIRQC + PCI_BDF(0, 24, 0) INTC PIRQD + PCI_BDF(0, 24, 0) INTD PIRQA + PCI_BDF(0, 25, 0) INTA PIRQC + PCI_BDF(0, 25, 0) INTB PIRQD + PCI_BDF(0, 25, 0) INTC PIRQA + PCI_BDF(0, 25, 0) INTD PIRQB + PCI_BDF(0, 26, 0) INTA PIRQD + PCI_BDF(0, 26, 0) INTB PIRQA + PCI_BDF(0, 26, 0) INTC PIRQB + PCI_BDF(0, 26, 0) INTD PIRQC PCI_BDF(0, 27, 0) INTA PIRQG /* * Topcliff PCI devices -- cgit v1.2.1