From 8b1c7345c6d5ed20b6b5ec8db17a3282e592184d Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck Date: Tue, 12 Feb 2013 22:22:12 +0100 Subject: MIPS: start.S: unify and simplify reset vector handling Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck --- arch/mips/cpu/mips64/start.S | 47 ++++++++++++++++++++------------------------ 1 file changed, 21 insertions(+), 26 deletions(-) (limited to 'arch/mips/cpu/mips64') diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 15225945e9..c0ae41a18a 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -52,40 +52,40 @@ .globl _start .text _start: - .org 0x000 + /* U-boot entry point */ b reset nop - .org 0x080 - b romReserved - nop - .org 0x100 - b romReserved - nop - .org 0x180 - b romReserved - nop + .org 0x200 - b romReserved + /* TLB refill, 32 bit task */ +1: b 1b nop + .org 0x280 - b romReserved + /* XTLB refill, 64 bit task */ +1: b 1b nop + .org 0x300 - b romReserved + /* Cache error exception */ +1: b 1b nop + .org 0x380 - b romReserved + /* General exception */ +1: b 1b nop + + .org 0x400 + /* Catch interrupt exceptions */ +1: b 1b + nop + .org 0x480 - b romReserved + /* EJTAG debug exception */ +1: b 1b nop - /* - * We hope there are no more reserved vectors! - * 128 * 8 == 1024 == 0x400 - * so this is address R_VEC+0x400 == 0xbfc00400 - */ - .org 0x500 .align 4 reset: @@ -238,8 +238,3 @@ in_ram: move a1, s2 .end relocate_code - - /* Exception handlers */ -romReserved: - b romReserved - nop -- cgit v1.2.1