From 30088b09975017c90979d55bc0ead58ca424652f Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 21 Apr 2015 20:38:22 +0900 Subject: ARM: socfpga: move SoC headers to mach-socfpga/include/mach Move headers to mach-socfpga as well. Signed-off-by: Masahiro Yamada --- arch/arm/include/asm/arch-socfpga/clock_manager.h | 308 --------------------- arch/arm/include/asm/arch-socfpga/dwmmc.h | 12 - arch/arm/include/asm/arch-socfpga/fpga_manager.h | 77 ------ .../include/asm/arch-socfpga/freeze_controller.h | 49 ---- arch/arm/include/asm/arch-socfpga/gpio.h | 10 - arch/arm/include/asm/arch-socfpga/nic301.h | 195 ------------- arch/arm/include/asm/arch-socfpga/reset_manager.h | 48 ---- arch/arm/include/asm/arch-socfpga/scan_manager.h | 93 ------- arch/arm/include/asm/arch-socfpga/scu.h | 23 -- arch/arm/include/asm/arch-socfpga/sdram.h | 19 -- .../include/asm/arch-socfpga/socfpga_base_addrs.h | 62 ----- arch/arm/include/asm/arch-socfpga/system_manager.h | 147 ---------- arch/arm/include/asm/arch-socfpga/timer.h | 18 -- arch/arm/mach-socfpga/include/mach/clock_manager.h | 308 +++++++++++++++++++++ arch/arm/mach-socfpga/include/mach/dwmmc.h | 12 + arch/arm/mach-socfpga/include/mach/fpga_manager.h | 77 ++++++ .../mach-socfpga/include/mach/freeze_controller.h | 49 ++++ arch/arm/mach-socfpga/include/mach/gpio.h | 10 + arch/arm/mach-socfpga/include/mach/nic301.h | 195 +++++++++++++ arch/arm/mach-socfpga/include/mach/reset_manager.h | 48 ++++ arch/arm/mach-socfpga/include/mach/scan_manager.h | 93 +++++++ arch/arm/mach-socfpga/include/mach/scu.h | 23 ++ arch/arm/mach-socfpga/include/mach/sdram.h | 19 ++ .../mach-socfpga/include/mach/socfpga_base_addrs.h | 62 +++++ .../arm/mach-socfpga/include/mach/system_manager.h | 147 ++++++++++ arch/arm/mach-socfpga/include/mach/timer.h | 18 ++ 26 files changed, 1061 insertions(+), 1061 deletions(-) delete mode 100644 arch/arm/include/asm/arch-socfpga/clock_manager.h delete mode 100644 arch/arm/include/asm/arch-socfpga/dwmmc.h delete mode 100644 arch/arm/include/asm/arch-socfpga/fpga_manager.h delete mode 100644 arch/arm/include/asm/arch-socfpga/freeze_controller.h delete mode 100644 arch/arm/include/asm/arch-socfpga/gpio.h delete mode 100644 arch/arm/include/asm/arch-socfpga/nic301.h delete mode 100644 arch/arm/include/asm/arch-socfpga/reset_manager.h delete mode 100644 arch/arm/include/asm/arch-socfpga/scan_manager.h delete mode 100644 arch/arm/include/asm/arch-socfpga/scu.h delete mode 100644 arch/arm/include/asm/arch-socfpga/sdram.h delete mode 100644 arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h delete mode 100644 arch/arm/include/asm/arch-socfpga/system_manager.h delete mode 100644 arch/arm/include/asm/arch-socfpga/timer.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager.h create mode 100644 arch/arm/mach-socfpga/include/mach/dwmmc.h create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager.h create mode 100644 arch/arm/mach-socfpga/include/mach/freeze_controller.h create mode 100644 arch/arm/mach-socfpga/include/mach/gpio.h create mode 100644 arch/arm/mach-socfpga/include/mach/nic301.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager.h create mode 100644 arch/arm/mach-socfpga/include/mach/scan_manager.h create mode 100644 arch/arm/mach-socfpga/include/mach/scu.h create mode 100644 arch/arm/mach-socfpga/include/mach/sdram.h create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager.h create mode 100644 arch/arm/mach-socfpga/include/mach/timer.h (limited to 'arch/arm') diff --git a/arch/arm/include/asm/arch-socfpga/clock_manager.h b/arch/arm/include/asm/arch-socfpga/clock_manager.h deleted file mode 100644 index 5449726180..0000000000 --- a/arch/arm/include/asm/arch-socfpga/clock_manager.h +++ /dev/null @@ -1,308 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CLOCK_MANAGER_H_ -#define _CLOCK_MANAGER_H_ - -#ifndef __ASSEMBLER__ -/* Clock speed accessors */ -unsigned long cm_get_mpu_clk_hz(void); -unsigned long cm_get_sdram_clk_hz(void); -unsigned int cm_get_l4_sp_clk_hz(void); -unsigned int cm_get_mmc_controller_clk_hz(void); -unsigned int cm_get_qspi_controller_clk_hz(void); -unsigned int cm_get_spi_controller_clk_hz(void); -#endif - -typedef struct { - /* main group */ - uint32_t main_vco_base; - uint32_t mpuclk; - uint32_t mainclk; - uint32_t dbgatclk; - uint32_t mainqspiclk; - uint32_t mainnandsdmmcclk; - uint32_t cfg2fuser0clk; - uint32_t maindiv; - uint32_t dbgdiv; - uint32_t tracediv; - uint32_t l4src; - - /* peripheral group */ - uint32_t peri_vco_base; - uint32_t emac0clk; - uint32_t emac1clk; - uint32_t perqspiclk; - uint32_t pernandsdmmcclk; - uint32_t perbaseclk; - uint32_t s2fuser1clk; - uint32_t perdiv; - uint32_t gpiodiv; - uint32_t persrc; - - /* sdram pll group */ - uint32_t sdram_vco_base; - uint32_t ddrdqsclk; - uint32_t ddr2xdqsclk; - uint32_t ddrdqclk; - uint32_t s2fuser2clk; -} cm_config_t; - -extern void cm_basic_init(const cm_config_t *cfg); - -struct socfpga_clock_manager_main_pll { - u32 vco; - u32 misc; - u32 mpuclk; - u32 mainclk; - u32 dbgatclk; - u32 mainqspiclk; - u32 mainnandsdmmcclk; - u32 cfgs2fuser0clk; - u32 en; - u32 maindiv; - u32 dbgdiv; - u32 tracediv; - u32 l4src; - u32 stat; - u32 _pad_0x38_0x40[2]; -}; - -struct socfpga_clock_manager_per_pll { - u32 vco; - u32 misc; - u32 emac0clk; - u32 emac1clk; - u32 perqspiclk; - u32 pernandsdmmcclk; - u32 perbaseclk; - u32 s2fuser1clk; - u32 en; - u32 div; - u32 gpiodiv; - u32 src; - u32 stat; - u32 _pad_0x34_0x40[3]; -}; - -struct socfpga_clock_manager_sdr_pll { - u32 vco; - u32 ctrl; - u32 ddrdqsclk; - u32 ddr2xdqsclk; - u32 ddrdqclk; - u32 s2fuser2clk; - u32 en; - u32 stat; -}; - -struct socfpga_clock_manager_altera { - u32 mpuclk; - u32 mainclk; -}; - -struct socfpga_clock_manager { - u32 ctrl; - u32 bypass; - u32 inter; - u32 intren; - u32 dbctrl; - u32 stat; - u32 _pad_0x18_0x3f[10]; - struct socfpga_clock_manager_main_pll main_pll; - struct socfpga_clock_manager_per_pll per_pll; - struct socfpga_clock_manager_sdr_pll sdr_pll; - struct socfpga_clock_manager_altera altera; - u32 _pad_0xe8_0x200[70]; -}; - -#define CLKMGR_CTRL_SAFEMODE (1 << 0) -#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 - -#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) -#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 -#define CLKMGR_BYPASS_PERPLL (1 << 3) -#define CLKMGR_BYPASS_PERPLL_OFFSET 3 -#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) -#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 -#define CLKMGR_BYPASS_SDRPLL (1 << 1) -#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 -#define CLKMGR_BYPASS_MAINPLL (1 << 0) -#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 - -#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 -#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 -#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 -#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 -#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 -#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 - -#define CLKMGR_STAT_BUSY (1 << 0) - -/* Main PLL */ -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) -#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 -#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) -#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 -#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) -#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 -#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d - -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 -#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff - -#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 -#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 -#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 -#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 -#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 -#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 - -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 -#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 -#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 - -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 -#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c - -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 -#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 - -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) -#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) -#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 -#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 -#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 -#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 - -/* Per PLL */ -#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 -#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 -#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 -#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 -#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 - -#define CLKMGR_VCO_SSRC_EOSC1 0x0 -#define CLKMGR_VCO_SSRC_EOSC2 0x1 -#define CLKMGR_VCO_SSRC_F2S 0x2 - -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 -#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff - -#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 -#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 - -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 -#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 -#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 -#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 -#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 -#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 - -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 -#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff - -#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 -#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c -#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 -#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 -#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 -#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 -#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 -#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 -#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 -#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 -#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 -#define CLKMGR_QSPI_CLK_SRC_PER 0x2 - -/* SDR PLL */ -#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 -#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 -#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 -#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) -#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 -#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 -#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 -#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d -#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 -#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 - -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 - -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 -#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 - -#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/dwmmc.h b/arch/arm/include/asm/arch-socfpga/dwmmc.h deleted file mode 100644 index 945eb646ce..0000000000 --- a/arch/arm/include/asm/arch-socfpga/dwmmc.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * (C) Copyright 2013 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_DWMMC_H_ -#define _SOCFPGA_DWMMC_H_ - -extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); - -#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/fpga_manager.h b/arch/arm/include/asm/arch-socfpga/fpga_manager.h deleted file mode 100644 index a077e2284e..0000000000 --- a/arch/arm/include/asm/arch-socfpga/fpga_manager.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FPGA_MANAGER_H_ -#define _FPGA_MANAGER_H_ - -#include - -struct socfpga_fpga_manager { - /* FPGA Manager Module */ - u32 stat; /* 0x00 */ - u32 ctrl; - u32 dclkcnt; - u32 dclkstat; - u32 gpo; /* 0x10 */ - u32 gpi; - u32 misci; /* 0x18 */ - u32 _pad_0x1c_0x82c[517]; - - /* Configuration Monitor (MON) Registers */ - u32 gpio_inten; /* 0x830 */ - u32 gpio_intmask; - u32 gpio_inttype_level; - u32 gpio_int_polarity; - u32 gpio_intstatus; /* 0x840 */ - u32 gpio_raw_intstatus; - u32 _pad_0x848; - u32 gpio_porta_eoi; - u32 gpio_ext_porta; /* 0x850 */ - u32 _pad_0x854_0x85c[3]; - u32 gpio_1s_sync; /* 0x860 */ - u32 _pad_0x864_0x868[2]; - u32 gpio_ver_id_code; - u32 gpio_config_reg2; /* 0x870 */ - u32 gpio_config_reg1; -}; - -#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3 - -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 - -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 - -/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 - -/* FPGA CD Ratio Value */ -#define CDRATIO_x1 0x0 -#define CDRATIO_x2 0x1 -#define CDRATIO_x4 0x2 -#define CDRATIO_x8 0x3 - -/* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void); -int fpgamgr_get_mode(void); - -#endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h deleted file mode 100644 index f19ad87717..0000000000 --- a/arch/arm/include/asm/arch-socfpga/freeze_controller.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _FREEZE_CONTROLLER_H_ -#define _FREEZE_CONTROLLER_H_ - -struct socfpga_freeze_controller { - u32 vioctrl; - u32 padding[3]; - u32 hioctrl; - u32 src; - u32 hwctrl; -}; - -#define FREEZE_CHANNEL_NUM (4) - -typedef enum { - FREEZE_CTRL_FROZEN = 0, - FREEZE_CTRL_THAWED = 1 -} FREEZE_CTRL_CHAN_STATE; - -#define SYSMGR_FRZCTRL_ADDRESS 0x40 -#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 -#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 -#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 -#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 -#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 -#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 -#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 -#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 -#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 -#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 -#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 -#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 -#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 -#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 -#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 - -void sys_mgr_frzctrl_freeze_req(void); -void sys_mgr_frzctrl_thaw_req(void); - -#endif /* _FREEZE_CONTROLLER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/gpio.h b/arch/arm/include/asm/arch-socfpga/gpio.h deleted file mode 100644 index 6c61f188bc..0000000000 --- a/arch/arm/include/asm/arch-socfpga/gpio.h +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2014 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_GPIO_H -#define _SOCFPGA_GPIO_H - -#endif /* _SOCFPGA_GPIO_H */ diff --git a/arch/arm/include/asm/arch-socfpga/nic301.h b/arch/arm/include/asm/arch-socfpga/nic301.h deleted file mode 100644 index 3c8ab31ffb..0000000000 --- a/arch/arm/include/asm/arch-socfpga/nic301.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _NIC301_REGISTERS_H_ -#define _NIC301_REGISTERS_H_ - -struct nic301_registers { - u32 remap; /* 0x0 */ - /* Security Register Group */ - u32 _pad_0x4_0x8[1]; - u32 l4main; - u32 l4sp; - u32 l4mp; /* 0x10 */ - u32 l4osc1; - u32 l4spim; - u32 stm; - u32 lwhps2fpgaregs; /* 0x20 */ - u32 _pad_0x24_0x28[1]; - u32 usb1; - u32 nanddata; - u32 _pad_0x30_0x80[20]; - u32 usb0; /* 0x80 */ - u32 nandregs; - u32 qspidata; - u32 fpgamgrdata; - u32 hps2fpgaregs; /* 0x90 */ - u32 acp; - u32 rom; - u32 ocram; - u32 sdrdata; /* 0xA0 */ - u32 _pad_0xa4_0x1fd0[1995]; - /* ID Register Group */ - u32 periph_id_4; /* 0x1FD0 */ - u32 _pad_0x1fd4_0x1fe0[3]; - u32 periph_id_0; /* 0x1FE0 */ - u32 periph_id_1; - u32 periph_id_2; - u32 periph_id_3; - u32 comp_id_0; /* 0x1FF0 */ - u32 comp_id_1; - u32 comp_id_2; - u32 comp_id_3; - u32 _pad_0x2000_0x2008[2]; - /* L4 MAIN */ - u32 l4main_fn_mod_bm_iss; - u32 _pad_0x200c_0x3008[1023]; - /* L4 SP */ - u32 l4sp_fn_mod_bm_iss; - u32 _pad_0x300c_0x4008[1023]; - /* L4 MP */ - u32 l4mp_fn_mod_bm_iss; - u32 _pad_0x400c_0x5008[1023]; - /* L4 OSC1 */ - u32 l4osc_fn_mod_bm_iss; - u32 _pad_0x500c_0x6008[1023]; - /* L4 SPIM */ - u32 l4spim_fn_mod_bm_iss; - u32 _pad_0x600c_0x7008[1023]; - /* STM */ - u32 stm_fn_mod_bm_iss; - u32 _pad_0x700c_0x7108[63]; - u32 stm_fn_mod; - u32 _pad_0x710c_0x8008[959]; - /* LWHPS2FPGA */ - u32 lwhps2fpga_fn_mod_bm_iss; - u32 _pad_0x800c_0x8108[63]; - u32 lwhps2fpga_fn_mod; - u32 _pad_0x810c_0xa008[1983]; - /* USB1 */ - u32 usb1_fn_mod_bm_iss; - u32 _pad_0xa00c_0xa044[14]; - u32 usb1_ahb_cntl; - u32 _pad_0xa048_0xb008[1008]; - /* NANDDATA */ - u32 nanddata_fn_mod_bm_iss; - u32 _pad_0xb00c_0xb108[63]; - u32 nanddata_fn_mod; - u32 _pad_0xb10c_0x20008[21439]; - /* USB0 */ - u32 usb0_fn_mod_bm_iss; - u32 _pad_0x2000c_0x20044[14]; - u32 usb0_ahb_cntl; - u32 _pad_0x20048_0x21008[1008]; - /* NANDREGS */ - u32 nandregs_fn_mod_bm_iss; - u32 _pad_0x2100c_0x21108[63]; - u32 nandregs_fn_mod; - u32 _pad_0x2110c_0x22008[959]; - /* QSPIDATA */ - u32 qspidata_fn_mod_bm_iss; - u32 _pad_0x2200c_0x22044[14]; - u32 qspidata_ahb_cntl; - u32 _pad_0x22048_0x23008[1008]; - /* FPGAMGRDATA */ - u32 fpgamgrdata_fn_mod_bm_iss; - u32 _pad_0x2300c_0x23040[13]; - u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ - u32 _pad_0x23044_0x23108[49]; - u32 fn_mod; - u32 _pad_0x2310c_0x24008[959]; - /* HPS2FPGA */ - u32 hps2fpga_fn_mod_bm_iss; - u32 _pad_0x2400c_0x24040[13]; - u32 hps2fpga_wr_tidemark; /* 0x24040 */ - u32 _pad_0x24044_0x24108[49]; - u32 hps2fpga_fn_mod; - u32 _pad_0x2410c_0x25008[959]; - /* ACP */ - u32 acp_fn_mod_bm_iss; - u32 _pad_0x2500c_0x25108[63]; - u32 acp_fn_mod; - u32 _pad_0x2510c_0x26008[959]; - /* Boot ROM */ - u32 bootrom_fn_mod_bm_iss; - u32 _pad_0x2600c_0x26108[63]; - u32 bootrom_fn_mod; - u32 _pad_0x2610c_0x27008[959]; - /* On-chip RAM */ - u32 ocram_fn_mod_bm_iss; - u32 _pad_0x2700c_0x27040[13]; - u32 ocram_wr_tidemark; /* 0x27040 */ - u32 _pad_0x27044_0x27108[49]; - u32 ocram_fn_mod; - u32 _pad_0x2710c_0x42024[27590]; - /* DAP */ - u32 dap_fn_mod2; - u32 dap_fn_mod_ahb; - u32 _pad_0x4202c_0x42100[53]; - u32 dap_read_qos; /* 0x42100 */ - u32 dap_write_qos; - u32 dap_fn_mod; - u32 _pad_0x4210c_0x43100[1021]; - /* MPU */ - u32 mpu_read_qos; /* 0x43100 */ - u32 mpu_write_qos; - u32 mpu_fn_mod; - u32 _pad_0x4310c_0x44028[967]; - /* SDMMC */ - u32 sdmmc_fn_mod_ahb; - u32 _pad_0x4402c_0x44100[53]; - u32 sdmmc_read_qos; /* 0x44100 */ - u32 sdmmc_write_qos; - u32 sdmmc_fn_mod; - u32 _pad_0x4410c_0x45100[1021]; - /* DMA */ - u32 dma_read_qos; /* 0x45100 */ - u32 dma_write_qos; - u32 dma_fn_mod; - u32 _pad_0x4510c_0x46040[973]; - /* FPGA2HPS */ - u32 fpga2hps_wr_tidemark; /* 0x46040 */ - u32 _pad_0x46044_0x46100[47]; - u32 fpga2hps_read_qos; /* 0x46100 */ - u32 fpga2hps_write_qos; - u32 fpga2hps_fn_mod; - u32 _pad_0x4610c_0x47100[1021]; - /* ETR */ - u32 etr_read_qos; /* 0x47100 */ - u32 etr_write_qos; - u32 etr_fn_mod; - u32 _pad_0x4710c_0x48100[1021]; - /* EMAC0 */ - u32 emac0_read_qos; /* 0x48100 */ - u32 emac0_write_qos; - u32 emac0_fn_mod; - u32 _pad_0x4810c_0x49100[1021]; - /* EMAC1 */ - u32 emac1_read_qos; /* 0x49100 */ - u32 emac1_write_qos; - u32 emac1_fn_mod; - u32 _pad_0x4910c_0x4a028[967]; - /* USB0 */ - u32 usb0_fn_mod_ahb; - u32 _pad_0x4a02c_0x4a100[53]; - u32 usb0_read_qos; /* 0x4A100 */ - u32 usb0_write_qos; - u32 usb0_fn_mod; - u32 _pad_0x4a10c_0x4b100[1021]; - /* NAND */ - u32 nand_read_qos; /* 0x4B100 */ - u32 nand_write_qos; - u32 nand_fn_mod; - u32 _pad_0x4b10c_0x4c028[967]; - /* USB1 */ - u32 usb1_fn_mod_ahb; - u32 _pad_0x4c02c_0x4c100[53]; - u32 usb1_read_qos; /* 0x4C100 */ - u32 usb1_write_qos; - u32 usb1_fn_mod; -}; - -#endif /* _NIC301_REGISTERS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/reset_manager.h b/arch/arm/include/asm/arch-socfpga/reset_manager.h deleted file mode 100644 index d63a285091..0000000000 --- a/arch/arm/include/asm/arch-socfpga/reset_manager.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _RESET_MANAGER_H_ -#define _RESET_MANAGER_H_ - -void reset_cpu(ulong addr); -void reset_deassert_peripherals_handoff(void); - -void socfpga_bridges_reset(int enable); - -void socfpga_emac_reset(int enable); -void socfpga_watchdog_reset(void); -void socfpga_spim_enable(void); -void socfpga_uart0_enable(void); -void socfpga_sdram_enable(void); -void socfpga_osc1timer_enable(void); - -struct socfpga_reset_manager { - u32 status; - u32 ctrl; - u32 counts; - u32 padding1; - u32 mpu_mod_reset; - u32 per_mod_reset; - u32 per2_mod_reset; - u32 brg_mod_reset; -}; - -#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 -#else -#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 -#endif - -#define RSTMGR_PERMODRST_EMAC0_LSB 0 -#define RSTMGR_PERMODRST_EMAC1_LSB 1 -#define RSTMGR_PERMODRST_L4WD0_LSB 6 -#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 -#define RSTMGR_PERMODRST_UART0_LSB 16 -#define RSTMGR_PERMODRST_SPIM0_LSB 18 -#define RSTMGR_PERMODRST_SPIM1_LSB 19 -#define RSTMGR_PERMODRST_SDR_LSB 29 - -#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h deleted file mode 100644 index 1155fd3dec..0000000000 --- a/arch/arm/include/asm/arch-socfpga/scan_manager.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SCAN_MANAGER_H_ -#define _SCAN_MANAGER_H_ - -struct socfpga_scan_manager { - u32 stat; - u32 en; - u32 padding[2]; - u32 fifo_single_byte; - u32 fifo_double_byte; - u32 fifo_triple_byte; - u32 fifo_quad_byte; -}; - -/* - * Shift count to get number of IO scan chain data in granularity - * of 128-bit ( N / 128 ) - */ -#define IO_SCAN_CHAIN_128BIT_SHIFT 7 - -/* - * Mask to get residual IO scan chain data in - * granularity of 128-bit ( N mod 128 ) - */ -#define IO_SCAN_CHAIN_128BIT_MASK 0x7F - -/* - * Shift count to get number of IO scan chain - * data in granularity of 32-bit ( N / 32 ) - */ -#define IO_SCAN_CHAIN_32BIT_SHIFT 5 - -/* - * Mask to get residual IO scan chain data in - * granularity of 32-bit ( N mod 32 ) - */ -#define IO_SCAN_CHAIN_32BIT_MASK 0x1F - -/* Byte mask */ -#define IO_SCAN_CHAIN_BYTE_MASK 0xFF - -/* 24-bits (3 bytes) IO scan chain payload definition */ -#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 - -/* - * Maximum length of TDI_TDO packet payload is 128 bits, - * represented by (length - 1) in TDI_TDO header - */ -#define TDI_TDO_MAX_PAYLOAD 127 - -/* TDI_TDO packet header for IO scan chain program */ -#define TDI_TDO_HEADER_FIRST_BYTE 0x80 - -/* Position of second command byte for TDI_TDO packet */ -#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 - -/* - * Maximum polling loop to wait for IO scan chain engine - * becomes idle to prevent infinite loop - */ -#define SCAN_MAX_DELAY 100 - -#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) -#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) - -/* - * Program HPS IO Scan Chain - * io_scan_chain_id - IO scan chain ID - * io_scan_chain_len_in_bits - IO scan chain length in bits - * iocsr_scan_chain - IO scan chain table - */ -uint32_t scan_mgr_io_scan_chain_prg( - uint32_t io_scan_chain_id, - uint32_t io_scan_chain_len_in_bits, - const uint32_t *iocsr_scan_chain); - -extern const uint32_t iocsr_scan_chain0_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; -extern const uint32_t iocsr_scan_chain1_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; -extern const uint32_t iocsr_scan_chain2_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; -extern const uint32_t iocsr_scan_chain3_table[ - ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; - -int scan_mgr_configure_iocsr(void); - -#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/scu.h b/arch/arm/include/asm/arch-socfpga/scu.h deleted file mode 100644 index 7a5b07416d..0000000000 --- a/arch/arm/include/asm/arch-socfpga/scu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2014 Marek Vasut - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __SOCFPGA_SCU_H__ -#define __SOCFPGA_SCU_H__ - -struct scu_registers { - u32 ctrl; /* 0x00 */ - u32 cfg; - u32 cpsr; - u32 iassr; - u32 _pad_0x10_0x3c[12]; /* 0x10 */ - u32 fsar; /* 0x40 */ - u32 fear; - u32 _pad_0x48_0x50[2]; - u32 acr; /* 0x54 */ - u32 sacr; -}; - -#endif /* __SOCFPGA_SCU_H__ */ diff --git a/arch/arm/include/asm/arch-socfpga/sdram.h b/arch/arm/include/asm/arch-socfpga/sdram.h deleted file mode 100644 index 4f6489dff6..0000000000 --- a/arch/arm/include/asm/arch-socfpga/sdram.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (C) 2015 Marek Vasut - * - * FIXME: This file contains temporary stub functions and is here - * only until these functions are properly merged into - * mainline. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ARCH_SDRAM_H__ -#define __ARCH_SDRAM_H__ - -/* function declaration */ -inline unsigned long sdram_calculate_size(void) { return 0; } -inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } -inline int sdram_calibration_full(void) { return 0; } - -#endif /* __ARCH_SDRAM_H__ */ diff --git a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h b/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h deleted file mode 100644 index 6534283331..0000000000 --- a/arch/arm/include/asm/arch-socfpga/socfpga_base_addrs.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_BASE_ADDRS_H_ -#define _SOCFPGA_BASE_ADDRS_H_ - -#define SOCFPGA_STM_ADDRESS 0xfc000000 -#define SOCFPGA_DAP_ADDRESS 0xff000000 -#define SOCFPGA_EMAC0_ADDRESS 0xff700000 -#define SOCFPGA_EMAC1_ADDRESS 0xff702000 -#define SOCFPGA_SDMMC_ADDRESS 0xff704000 -#define SOCFPGA_QSPI_ADDRESS 0xff705000 -#define SOCFPGA_GPIO0_ADDRESS 0xff708000 -#define SOCFPGA_GPIO1_ADDRESS 0xff709000 -#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 -#define SOCFPGA_L3REGS_ADDRESS 0xff800000 -#define SOCFPGA_USB0_ADDRESS 0xffb00000 -#define SOCFPGA_USB1_ADDRESS 0xffb40000 -#define SOCFPGA_CAN0_ADDRESS 0xffc00000 -#define SOCFPGA_CAN1_ADDRESS 0xffc01000 -#define SOCFPGA_UART0_ADDRESS 0xffc02000 -#define SOCFPGA_UART1_ADDRESS 0xffc03000 -#define SOCFPGA_I2C0_ADDRESS 0xffc04000 -#define SOCFPGA_I2C1_ADDRESS 0xffc05000 -#define SOCFPGA_I2C2_ADDRESS 0xffc06000 -#define SOCFPGA_I2C3_ADDRESS 0xffc07000 -#define SOCFPGA_SDR_ADDRESS 0xffc20000 -#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 -#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 -#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 -#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 -#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 -#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 -#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 -#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 -#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 -#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 -#define SOCFPGA_ROM_ADDRESS 0xfffd0000 -#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 -#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 -#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 -#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 -#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 -#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 -#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 -#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 -#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 -#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 -#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 -#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 -#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 -#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 -#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 -#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 -#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 -#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 -#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 - -#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/system_manager.h b/arch/arm/include/asm/arch-socfpga/system_manager.h deleted file mode 100644 index 51d9815778..0000000000 --- a/arch/arm/include/asm/arch-socfpga/system_manager.h +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (C) 2013 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SYSTEM_MANAGER_H_ -#define _SYSTEM_MANAGER_H_ - -#ifndef __ASSEMBLY__ - -void sysmgr_pinmux_init(void); -void sysmgr_enable_warmrstcfgio(void); - -/* declaration for handoff table type */ -extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; - -#endif - -struct socfpga_system_manager { - /* System Manager Module */ - u32 siliconid1; /* 0x00 */ - u32 siliconid2; - u32 _pad_0x8_0xf[2]; - u32 wddbg; /* 0x10 */ - u32 bootinfo; - u32 hpsinfo; - u32 parityinj; - /* FPGA Interface Group */ - u32 fpgaintfgrp_gbl; /* 0x20 */ - u32 fpgaintfgrp_indiv; - u32 fpgaintfgrp_module; - u32 _pad_0x2c_0x2f; - /* Scan Manager Group */ - u32 scanmgrgrp_ctrl; /* 0x30 */ - u32 _pad_0x34_0x3f[3]; - /* Freeze Control Group */ - u32 frzctrl_vioctrl; /* 0x40 */ - u32 _pad_0x44_0x4f[3]; - u32 frzctrl_hioctrl; /* 0x50 */ - u32 frzctrl_src; - u32 frzctrl_hwctrl; - u32 _pad_0x5c_0x5f; - /* EMAC Group */ - u32 emacgrp_ctrl; /* 0x60 */ - u32 emacgrp_l3master; - u32 _pad_0x68_0x6f[2]; - /* DMA Controller Group */ - u32 dmagrp_ctrl; /* 0x70 */ - u32 dmagrp_persecurity; - u32 _pad_0x78_0x7f[2]; - /* Preloader (initial software) Group */ - u32 iswgrp_handoff[8]; /* 0x80 */ - u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ - /* Boot ROM Code Register Group */ - u32 romcodegrp_ctrl; /* 0xc0 */ - u32 romcodegrp_cpu1startaddr; - u32 romcodegrp_initswstate; - u32 romcodegrp_initswlastld; - u32 romcodegrp_bootromswstate; /* 0xd0 */ - u32 __pad_0xd4_0xdf[3]; - /* Warm Boot from On-Chip RAM Group */ - u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ - u32 romcodegrp_warmramgrp_datastart; - u32 romcodegrp_warmramgrp_length; - u32 romcodegrp_warmramgrp_execution; - u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ - u32 __pad_0xf4_0xff[3]; - /* Boot ROM Hardware Register Group */ - u32 romhwgrp_ctrl; /* 0x100 */ - u32 _pad_0x104_0x107; - /* SDMMC Controller Group */ - u32 sdmmcgrp_ctrl; - u32 sdmmcgrp_l3master; - /* NAND Flash Controller Register Group */ - u32 nandgrp_bootstrap; /* 0x110 */ - u32 nandgrp_l3master; - /* USB Controller Group */ - u32 usbgrp_l3master; - u32 _pad_0x11c_0x13f[9]; - /* ECC Management Register Group */ - u32 eccgrp_l2; /* 0x140 */ - u32 eccgrp_ocram; - u32 eccgrp_usb0; - u32 eccgrp_usb1; - u32 eccgrp_emac0; /* 0x150 */ - u32 eccgrp_emac1; - u32 eccgrp_dma; - u32 eccgrp_can0; - u32 eccgrp_can1; /* 0x160 */ - u32 eccgrp_nand; - u32 eccgrp_qspi; - u32 eccgrp_sdmmc; - u32 _pad_0x170_0x3ff[164]; - /* Pin Mux Control Group */ - u32 emacio[20]; /* 0x400 */ - u32 flashio[12]; /* 0x450 */ - u32 generalio[28]; /* 0x480 */ - u32 _pad_0x4f0_0x4ff[4]; - u32 mixed1io[22]; /* 0x500 */ - u32 mixed2io[8]; /* 0x558 */ - u32 gplinmux[23]; /* 0x578 */ - u32 gplmux[71]; /* 0x5d4 */ - u32 nandusefpga; /* 0x6f0 */ - u32 _pad_0x6f4; - u32 rgmii1usefpga; /* 0x6f8 */ - u32 _pad_0x6fc_0x700[2]; - u32 i2c0usefpga; /* 0x704 */ - u32 sdmmcusefpga; /* 0x708 */ - u32 _pad_0x70c_0x710[2]; - u32 rgmii0usefpga; /* 0x714 */ - u32 _pad_0x718_0x720[3]; - u32 i2c3usefpga; /* 0x724 */ - u32 i2c2usefpga; /* 0x728 */ - u32 i2c1usefpga; /* 0x72c */ - u32 spim1usefpga; /* 0x730 */ - u32 _pad_0x734; - u32 spim0usefpga; /* 0x738 */ -}; - -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) -#define SYSMGR_ECC_OCRAM_EN (1 << 0) -#define SYSMGR_ECC_OCRAM_SERR (1 << 3) -#define SYSMGR_ECC_OCRAM_DERR (1 << 4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1 -#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) -#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) -#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) -#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) -#define SYSMGR_FPGAINTF_NAND (1 << 4) -#define SYSMGR_FPGAINTF_SDMMC (1 << 5) - -/* FIXME: This is questionable macro. */ -#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ - ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) - -/* EMAC Group Bit definitions */ -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 - -#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 - -#endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/include/asm/arch-socfpga/timer.h b/arch/arm/include/asm/arch-socfpga/timer.h deleted file mode 100644 index ee6969bac8..0000000000 --- a/arch/arm/include/asm/arch-socfpga/timer.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2012 Altera Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SOCFPGA_TIMER_H_ -#define _SOCFPGA_TIMER_H_ - -struct socfpga_timer { - u32 load_val; - u32 curr_val; - u32 ctrl; - u32 eoi; - u32 int_stat; -}; - -#endif diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h new file mode 100644 index 0000000000..5449726180 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_MANAGER_H_ +#define _CLOCK_MANAGER_H_ + +#ifndef __ASSEMBLER__ +/* Clock speed accessors */ +unsigned long cm_get_mpu_clk_hz(void); +unsigned long cm_get_sdram_clk_hz(void); +unsigned int cm_get_l4_sp_clk_hz(void); +unsigned int cm_get_mmc_controller_clk_hz(void); +unsigned int cm_get_qspi_controller_clk_hz(void); +unsigned int cm_get_spi_controller_clk_hz(void); +#endif + +typedef struct { + /* main group */ + uint32_t main_vco_base; + uint32_t mpuclk; + uint32_t mainclk; + uint32_t dbgatclk; + uint32_t mainqspiclk; + uint32_t mainnandsdmmcclk; + uint32_t cfg2fuser0clk; + uint32_t maindiv; + uint32_t dbgdiv; + uint32_t tracediv; + uint32_t l4src; + + /* peripheral group */ + uint32_t peri_vco_base; + uint32_t emac0clk; + uint32_t emac1clk; + uint32_t perqspiclk; + uint32_t pernandsdmmcclk; + uint32_t perbaseclk; + uint32_t s2fuser1clk; + uint32_t perdiv; + uint32_t gpiodiv; + uint32_t persrc; + + /* sdram pll group */ + uint32_t sdram_vco_base; + uint32_t ddrdqsclk; + uint32_t ddr2xdqsclk; + uint32_t ddrdqclk; + uint32_t s2fuser2clk; +} cm_config_t; + +extern void cm_basic_init(const cm_config_t *cfg); + +struct socfpga_clock_manager_main_pll { + u32 vco; + u32 misc; + u32 mpuclk; + u32 mainclk; + u32 dbgatclk; + u32 mainqspiclk; + u32 mainnandsdmmcclk; + u32 cfgs2fuser0clk; + u32 en; + u32 maindiv; + u32 dbgdiv; + u32 tracediv; + u32 l4src; + u32 stat; + u32 _pad_0x38_0x40[2]; +}; + +struct socfpga_clock_manager_per_pll { + u32 vco; + u32 misc; + u32 emac0clk; + u32 emac1clk; + u32 perqspiclk; + u32 pernandsdmmcclk; + u32 perbaseclk; + u32 s2fuser1clk; + u32 en; + u32 div; + u32 gpiodiv; + u32 src; + u32 stat; + u32 _pad_0x34_0x40[3]; +}; + +struct socfpga_clock_manager_sdr_pll { + u32 vco; + u32 ctrl; + u32 ddrdqsclk; + u32 ddr2xdqsclk; + u32 ddrdqclk; + u32 s2fuser2clk; + u32 en; + u32 stat; +}; + +struct socfpga_clock_manager_altera { + u32 mpuclk; + u32 mainclk; +}; + +struct socfpga_clock_manager { + u32 ctrl; + u32 bypass; + u32 inter; + u32 intren; + u32 dbctrl; + u32 stat; + u32 _pad_0x18_0x3f[10]; + struct socfpga_clock_manager_main_pll main_pll; + struct socfpga_clock_manager_per_pll per_pll; + struct socfpga_clock_manager_sdr_pll sdr_pll; + struct socfpga_clock_manager_altera altera; + u32 _pad_0xe8_0x200[70]; +}; + +#define CLKMGR_CTRL_SAFEMODE (1 << 0) +#define CLKMGR_CTRL_SAFEMODE_OFFSET 0 + +#define CLKMGR_BYPASS_PERPLLSRC (1 << 4) +#define CLKMGR_BYPASS_PERPLLSRC_OFFSET 4 +#define CLKMGR_BYPASS_PERPLL (1 << 3) +#define CLKMGR_BYPASS_PERPLL_OFFSET 3 +#define CLKMGR_BYPASS_SDRPLLSRC (1 << 2) +#define CLKMGR_BYPASS_SDRPLLSRC_OFFSET 2 +#define CLKMGR_BYPASS_SDRPLL (1 << 1) +#define CLKMGR_BYPASS_SDRPLL_OFFSET 1 +#define CLKMGR_BYPASS_MAINPLL (1 << 0) +#define CLKMGR_BYPASS_MAINPLL_OFFSET 0 + +#define CLKMGR_INTER_SDRPLLLOCKED_MASK 0x00000100 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000080 +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000040 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000010 +#define CLKMGR_INTER_SDRPLLLOST_MASK 0x00000020 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000008 + +#define CLKMGR_STAT_BUSY (1 << 0) + +/* Main PLL */ +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN (1 << 0) +#define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_MAINPLLGRP_VCO_EN (1 << 1) +#define CLKMGR_MAINPLLGRP_VCO_EN_OFFSET 1 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_MAINPLLGRP_VCO_PWRDN (1 << 2) +#define CLKMGR_MAINPLLGRP_VCO_PWRDN_OFFSET 2 +#define CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_MAINPLLGRP_VCO_RESET_VALUE 0x8001000d + +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MPUCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGATCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET 0 +#define CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK 0x00000010 +#define CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK 0x00000020 +#define CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK 0x00000080 +#define CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK 0x00000040 +#define CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK 0x00000004 +#define CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK 0x00000200 + +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_MASK 0x0000000c +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET 4 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_MASK 0x00000070 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET 7 +#define CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_MASK 0x00000380 + +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_MASK 0x00000003 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET 2 +#define CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_MASK 0x0000000c + +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET 0 +#define CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_MASK 0x00000007 + +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP (1 << 0) +#define CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET 0 +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP (1 << 1) +#define CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET 1 +#define CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE 0x00000000 +#define CLKMGR_L4_SP_CLK_SRC_MAINPLL 0x0 +#define CLKMGR_L4_SP_CLK_SRC_PERPLL 0x1 + +/* Per PLL */ +#define CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_PERPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_PERPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK 0x01000000 +#define CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_PSRC_MASK 0x00c00000 +#define CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_PERPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_PERPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_PERPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_VCO_SSRC_EOSC1 0x0 +#define CLKMGR_VCO_SSRC_EOSC2 0x1 +#define CLKMGR_VCO_SSRC_F2S 0x2 + +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC0CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_EMAC1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERQSPICLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_PERBASECLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET 0 +#define CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_MASK 0x000001ff + +#define CLKMGR_PERPLLGRP_EN_NANDCLK_MASK 0x00000400 +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000100 + +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET 6 +#define CLKMGR_PERPLLGRP_DIV_CAN0CLK_MASK 0x000001c0 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET 9 +#define CLKMGR_PERPLLGRP_DIV_CAN1CLK_MASK 0x00000e00 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET 3 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_DIV_USBCLK_MASK 0x00000007 + +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET 0 +#define CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_MASK 0x00ffffff + +#define CLKMGR_PERPLLGRP_SRC_NAND_OFFSET 2 +#define CLKMGR_PERPLLGRP_SRC_NAND_MASK 0x0000000c +#define CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET 4 +#define CLKMGR_PERPLLGRP_SRC_QSPI_MASK 0x00000030 +#define CLKMGR_PERPLLGRP_SRC_RESET_VALUE 0x00000015 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET 0 +#define CLKMGR_PERPLLGRP_SRC_SDMMC_MASK 0x00000003 +#define CLKMGR_SDMMC_CLK_SRC_F2S 0x0 +#define CLKMGR_SDMMC_CLK_SRC_MAIN 0x1 +#define CLKMGR_SDMMC_CLK_SRC_PER 0x2 +#define CLKMGR_QSPI_CLK_SRC_F2S 0x0 +#define CLKMGR_QSPI_CLK_SRC_MAIN 0x1 +#define CLKMGR_QSPI_CLK_SRC_PER 0x2 + +/* SDR PLL */ +#define CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET 16 +#define CLKMGR_SDRPLLGRP_VCO_DENOM_MASK 0x003f0000 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET 3 +#define CLKMGR_SDRPLLGRP_VCO_NUMER_MASK 0x0000fff8 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL (1 << 24) +#define CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_OFFSET 24 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_OFFSET 25 +#define CLKMGR_SDRPLLGRP_VCO_OUTRESET_MASK 0x7e000000 +#define CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK 0x80000000 +#define CLKMGR_SDRPLLGRP_VCO_RESET_VALUE 0x8001000d +#define CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET 22 +#define CLKMGR_SDRPLLGRP_VCO_SSRC_MASK 0x00c00000 + +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK 0x00000e00 + +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET 0 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK 0x000001ff +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET 9 +#define CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK 0x00000e00 + +#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/dwmmc.h b/arch/arm/mach-socfpga/include/mach/dwmmc.h new file mode 100644 index 0000000000..945eb646ce --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/dwmmc.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_DWMMC_H_ +#define _SOCFPGA_DWMMC_H_ + +extern int socfpga_dwmmc_init(u32 regbase, int bus_width, int index); + +#endif /* _SOCFPGA_SDMMC_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h new file mode 100644 index 0000000000..a077e2284e --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2012 Altera Corporation + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_H_ +#define _FPGA_MANAGER_H_ + +#include + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 +#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 +#define FPGAMGRREGS_CTRL_EN_MASK 0x1 +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +/* FPGA CD Ratio Value */ +#define CDRATIO_x1 0x0 +#define CDRATIO_x2 0x1 +#define CDRATIO_x4 0x2 +#define CDRATIO_x8 0x3 + +/* SoCFPGA support functions */ +int fpgamgr_test_fpga_ready(void); +int fpgamgr_poll_fpga_ready(void); +int fpgamgr_get_mode(void); + +#endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/freeze_controller.h b/arch/arm/mach-socfpga/include/mach/freeze_controller.h new file mode 100644 index 0000000000..f19ad87717 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/freeze_controller.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FREEZE_CONTROLLER_H_ +#define _FREEZE_CONTROLLER_H_ + +struct socfpga_freeze_controller { + u32 vioctrl; + u32 padding[3]; + u32 hioctrl; + u32 src; + u32 hwctrl; +}; + +#define FREEZE_CHANNEL_NUM (4) + +typedef enum { + FREEZE_CTRL_FROZEN = 0, + FREEZE_CTRL_THAWED = 1 +} FREEZE_CTRL_CHAN_STATE; + +#define SYSMGR_FRZCTRL_ADDRESS 0x40 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0 +#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1 +#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010 +#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008 +#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004 +#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002 +#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080 +#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040 +#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100 +#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2 +#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1 + +void sys_mgr_frzctrl_freeze_req(void); +void sys_mgr_frzctrl_thaw_req(void); + +#endif /* _FREEZE_CONTROLLER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/gpio.h b/arch/arm/mach-socfpga/include/mach/gpio.h new file mode 100644 index 0000000000..6c61f188bc --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Stefan Roese + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_GPIO_H +#define _SOCFPGA_GPIO_H + +#endif /* _SOCFPGA_GPIO_H */ diff --git a/arch/arm/mach-socfpga/include/mach/nic301.h b/arch/arm/mach-socfpga/include/mach/nic301.h new file mode 100644 index 0000000000..3c8ab31ffb --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/nic301.h @@ -0,0 +1,195 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _NIC301_REGISTERS_H_ +#define _NIC301_REGISTERS_H_ + +struct nic301_registers { + u32 remap; /* 0x0 */ + /* Security Register Group */ + u32 _pad_0x4_0x8[1]; + u32 l4main; + u32 l4sp; + u32 l4mp; /* 0x10 */ + u32 l4osc1; + u32 l4spim; + u32 stm; + u32 lwhps2fpgaregs; /* 0x20 */ + u32 _pad_0x24_0x28[1]; + u32 usb1; + u32 nanddata; + u32 _pad_0x30_0x80[20]; + u32 usb0; /* 0x80 */ + u32 nandregs; + u32 qspidata; + u32 fpgamgrdata; + u32 hps2fpgaregs; /* 0x90 */ + u32 acp; + u32 rom; + u32 ocram; + u32 sdrdata; /* 0xA0 */ + u32 _pad_0xa4_0x1fd0[1995]; + /* ID Register Group */ + u32 periph_id_4; /* 0x1FD0 */ + u32 _pad_0x1fd4_0x1fe0[3]; + u32 periph_id_0; /* 0x1FE0 */ + u32 periph_id_1; + u32 periph_id_2; + u32 periph_id_3; + u32 comp_id_0; /* 0x1FF0 */ + u32 comp_id_1; + u32 comp_id_2; + u32 comp_id_3; + u32 _pad_0x2000_0x2008[2]; + /* L4 MAIN */ + u32 l4main_fn_mod_bm_iss; + u32 _pad_0x200c_0x3008[1023]; + /* L4 SP */ + u32 l4sp_fn_mod_bm_iss; + u32 _pad_0x300c_0x4008[1023]; + /* L4 MP */ + u32 l4mp_fn_mod_bm_iss; + u32 _pad_0x400c_0x5008[1023]; + /* L4 OSC1 */ + u32 l4osc_fn_mod_bm_iss; + u32 _pad_0x500c_0x6008[1023]; + /* L4 SPIM */ + u32 l4spim_fn_mod_bm_iss; + u32 _pad_0x600c_0x7008[1023]; + /* STM */ + u32 stm_fn_mod_bm_iss; + u32 _pad_0x700c_0x7108[63]; + u32 stm_fn_mod; + u32 _pad_0x710c_0x8008[959]; + /* LWHPS2FPGA */ + u32 lwhps2fpga_fn_mod_bm_iss; + u32 _pad_0x800c_0x8108[63]; + u32 lwhps2fpga_fn_mod; + u32 _pad_0x810c_0xa008[1983]; + /* USB1 */ + u32 usb1_fn_mod_bm_iss; + u32 _pad_0xa00c_0xa044[14]; + u32 usb1_ahb_cntl; + u32 _pad_0xa048_0xb008[1008]; + /* NANDDATA */ + u32 nanddata_fn_mod_bm_iss; + u32 _pad_0xb00c_0xb108[63]; + u32 nanddata_fn_mod; + u32 _pad_0xb10c_0x20008[21439]; + /* USB0 */ + u32 usb0_fn_mod_bm_iss; + u32 _pad_0x2000c_0x20044[14]; + u32 usb0_ahb_cntl; + u32 _pad_0x20048_0x21008[1008]; + /* NANDREGS */ + u32 nandregs_fn_mod_bm_iss; + u32 _pad_0x2100c_0x21108[63]; + u32 nandregs_fn_mod; + u32 _pad_0x2110c_0x22008[959]; + /* QSPIDATA */ + u32 qspidata_fn_mod_bm_iss; + u32 _pad_0x2200c_0x22044[14]; + u32 qspidata_ahb_cntl; + u32 _pad_0x22048_0x23008[1008]; + /* FPGAMGRDATA */ + u32 fpgamgrdata_fn_mod_bm_iss; + u32 _pad_0x2300c_0x23040[13]; + u32 fpgamgrdata_wr_tidemark; /* 0x23040 */ + u32 _pad_0x23044_0x23108[49]; + u32 fn_mod; + u32 _pad_0x2310c_0x24008[959]; + /* HPS2FPGA */ + u32 hps2fpga_fn_mod_bm_iss; + u32 _pad_0x2400c_0x24040[13]; + u32 hps2fpga_wr_tidemark; /* 0x24040 */ + u32 _pad_0x24044_0x24108[49]; + u32 hps2fpga_fn_mod; + u32 _pad_0x2410c_0x25008[959]; + /* ACP */ + u32 acp_fn_mod_bm_iss; + u32 _pad_0x2500c_0x25108[63]; + u32 acp_fn_mod; + u32 _pad_0x2510c_0x26008[959]; + /* Boot ROM */ + u32 bootrom_fn_mod_bm_iss; + u32 _pad_0x2600c_0x26108[63]; + u32 bootrom_fn_mod; + u32 _pad_0x2610c_0x27008[959]; + /* On-chip RAM */ + u32 ocram_fn_mod_bm_iss; + u32 _pad_0x2700c_0x27040[13]; + u32 ocram_wr_tidemark; /* 0x27040 */ + u32 _pad_0x27044_0x27108[49]; + u32 ocram_fn_mod; + u32 _pad_0x2710c_0x42024[27590]; + /* DAP */ + u32 dap_fn_mod2; + u32 dap_fn_mod_ahb; + u32 _pad_0x4202c_0x42100[53]; + u32 dap_read_qos; /* 0x42100 */ + u32 dap_write_qos; + u32 dap_fn_mod; + u32 _pad_0x4210c_0x43100[1021]; + /* MPU */ + u32 mpu_read_qos; /* 0x43100 */ + u32 mpu_write_qos; + u32 mpu_fn_mod; + u32 _pad_0x4310c_0x44028[967]; + /* SDMMC */ + u32 sdmmc_fn_mod_ahb; + u32 _pad_0x4402c_0x44100[53]; + u32 sdmmc_read_qos; /* 0x44100 */ + u32 sdmmc_write_qos; + u32 sdmmc_fn_mod; + u32 _pad_0x4410c_0x45100[1021]; + /* DMA */ + u32 dma_read_qos; /* 0x45100 */ + u32 dma_write_qos; + u32 dma_fn_mod; + u32 _pad_0x4510c_0x46040[973]; + /* FPGA2HPS */ + u32 fpga2hps_wr_tidemark; /* 0x46040 */ + u32 _pad_0x46044_0x46100[47]; + u32 fpga2hps_read_qos; /* 0x46100 */ + u32 fpga2hps_write_qos; + u32 fpga2hps_fn_mod; + u32 _pad_0x4610c_0x47100[1021]; + /* ETR */ + u32 etr_read_qos; /* 0x47100 */ + u32 etr_write_qos; + u32 etr_fn_mod; + u32 _pad_0x4710c_0x48100[1021]; + /* EMAC0 */ + u32 emac0_read_qos; /* 0x48100 */ + u32 emac0_write_qos; + u32 emac0_fn_mod; + u32 _pad_0x4810c_0x49100[1021]; + /* EMAC1 */ + u32 emac1_read_qos; /* 0x49100 */ + u32 emac1_write_qos; + u32 emac1_fn_mod; + u32 _pad_0x4910c_0x4a028[967]; + /* USB0 */ + u32 usb0_fn_mod_ahb; + u32 _pad_0x4a02c_0x4a100[53]; + u32 usb0_read_qos; /* 0x4A100 */ + u32 usb0_write_qos; + u32 usb0_fn_mod; + u32 _pad_0x4a10c_0x4b100[1021]; + /* NAND */ + u32 nand_read_qos; /* 0x4B100 */ + u32 nand_write_qos; + u32 nand_fn_mod; + u32 _pad_0x4b10c_0x4c028[967]; + /* USB1 */ + u32 usb1_fn_mod_ahb; + u32 _pad_0x4c02c_0x4c100[53]; + u32 usb1_read_qos; /* 0x4C100 */ + u32 usb1_write_qos; + u32 usb1_fn_mod; +}; + +#endif /* _NIC301_REGISTERS_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h new file mode 100644 index 0000000000..d63a285091 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _RESET_MANAGER_H_ +#define _RESET_MANAGER_H_ + +void reset_cpu(ulong addr); +void reset_deassert_peripherals_handoff(void); + +void socfpga_bridges_reset(int enable); + +void socfpga_emac_reset(int enable); +void socfpga_watchdog_reset(void); +void socfpga_spim_enable(void); +void socfpga_uart0_enable(void); +void socfpga_sdram_enable(void); +void socfpga_osc1timer_enable(void); + +struct socfpga_reset_manager { + u32 status; + u32 ctrl; + u32 counts; + u32 padding1; + u32 mpu_mod_reset; + u32 per_mod_reset; + u32 per2_mod_reset; + u32 brg_mod_reset; +}; + +#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2 +#else +#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1 +#endif + +#define RSTMGR_PERMODRST_EMAC0_LSB 0 +#define RSTMGR_PERMODRST_EMAC1_LSB 1 +#define RSTMGR_PERMODRST_L4WD0_LSB 6 +#define RSTMGR_PERMODRST_OSC1TIMER0_LSB 8 +#define RSTMGR_PERMODRST_UART0_LSB 16 +#define RSTMGR_PERMODRST_SPIM0_LSB 18 +#define RSTMGR_PERMODRST_SPIM1_LSB 19 +#define RSTMGR_PERMODRST_SDR_LSB 29 + +#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/scan_manager.h b/arch/arm/mach-socfpga/include/mach/scan_manager.h new file mode 100644 index 0000000000..1155fd3dec --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/scan_manager.h @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SCAN_MANAGER_H_ +#define _SCAN_MANAGER_H_ + +struct socfpga_scan_manager { + u32 stat; + u32 en; + u32 padding[2]; + u32 fifo_single_byte; + u32 fifo_double_byte; + u32 fifo_triple_byte; + u32 fifo_quad_byte; +}; + +/* + * Shift count to get number of IO scan chain data in granularity + * of 128-bit ( N / 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_SHIFT 7 + +/* + * Mask to get residual IO scan chain data in + * granularity of 128-bit ( N mod 128 ) + */ +#define IO_SCAN_CHAIN_128BIT_MASK 0x7F + +/* + * Shift count to get number of IO scan chain + * data in granularity of 32-bit ( N / 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_SHIFT 5 + +/* + * Mask to get residual IO scan chain data in + * granularity of 32-bit ( N mod 32 ) + */ +#define IO_SCAN_CHAIN_32BIT_MASK 0x1F + +/* Byte mask */ +#define IO_SCAN_CHAIN_BYTE_MASK 0xFF + +/* 24-bits (3 bytes) IO scan chain payload definition */ +#define IO_SCAN_CHAIN_PAYLOAD_24BIT 24 + +/* + * Maximum length of TDI_TDO packet payload is 128 bits, + * represented by (length - 1) in TDI_TDO header + */ +#define TDI_TDO_MAX_PAYLOAD 127 + +/* TDI_TDO packet header for IO scan chain program */ +#define TDI_TDO_HEADER_FIRST_BYTE 0x80 + +/* Position of second command byte for TDI_TDO packet */ +#define TDI_TDO_HEADER_SECOND_BYTE_SHIFT 8 + +/* + * Maximum polling loop to wait for IO scan chain engine + * becomes idle to prevent infinite loop + */ +#define SCAN_MAX_DELAY 100 + +#define SCANMGR_STAT_ACTIVE_GET(x) (((x) & 0x80000000) >> 31) +#define SCANMGR_STAT_WFIFOCNT_GET(x) (((x) & 0x70000000) >> 28) + +/* + * Program HPS IO Scan Chain + * io_scan_chain_id - IO scan chain ID + * io_scan_chain_len_in_bits - IO scan chain length in bits + * iocsr_scan_chain - IO scan chain table + */ +uint32_t scan_mgr_io_scan_chain_prg( + uint32_t io_scan_chain_id, + uint32_t io_scan_chain_len_in_bits, + const uint32_t *iocsr_scan_chain); + +extern const uint32_t iocsr_scan_chain0_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain1_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain2_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH / 32) + 1)]; +extern const uint32_t iocsr_scan_chain3_table[ + ((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)]; + +int scan_mgr_configure_iocsr(void); + +#endif /* _SCAN_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/scu.h b/arch/arm/mach-socfpga/include/mach/scu.h new file mode 100644 index 0000000000..7a5b07416d --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/scu.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOCFPGA_SCU_H__ +#define __SOCFPGA_SCU_H__ + +struct scu_registers { + u32 ctrl; /* 0x00 */ + u32 cfg; + u32 cpsr; + u32 iassr; + u32 _pad_0x10_0x3c[12]; /* 0x10 */ + u32 fsar; /* 0x40 */ + u32 fear; + u32 _pad_0x48_0x50[2]; + u32 acr; /* 0x54 */ + u32 sacr; +}; + +#endif /* __SOCFPGA_SCU_H__ */ diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h new file mode 100644 index 0000000000..4f6489dff6 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015 Marek Vasut + * + * FIXME: This file contains temporary stub functions and is here + * only until these functions are properly merged into + * mainline. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ARCH_SDRAM_H__ +#define __ARCH_SDRAM_H__ + +/* function declaration */ +inline unsigned long sdram_calculate_size(void) { return 0; } +inline unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg) { return 0; } +inline int sdram_calibration_full(void) { return 0; } + +#endif /* __ARCH_SDRAM_H__ */ diff --git a/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h b/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h new file mode 100644 index 0000000000..6534283331 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/socfpga_base_addrs.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_BASE_ADDRS_H_ +#define _SOCFPGA_BASE_ADDRS_H_ + +#define SOCFPGA_STM_ADDRESS 0xfc000000 +#define SOCFPGA_DAP_ADDRESS 0xff000000 +#define SOCFPGA_EMAC0_ADDRESS 0xff700000 +#define SOCFPGA_EMAC1_ADDRESS 0xff702000 +#define SOCFPGA_SDMMC_ADDRESS 0xff704000 +#define SOCFPGA_QSPI_ADDRESS 0xff705000 +#define SOCFPGA_GPIO0_ADDRESS 0xff708000 +#define SOCFPGA_GPIO1_ADDRESS 0xff709000 +#define SOCFPGA_GPIO2_ADDRESS 0xff70a000 +#define SOCFPGA_L3REGS_ADDRESS 0xff800000 +#define SOCFPGA_USB0_ADDRESS 0xffb00000 +#define SOCFPGA_USB1_ADDRESS 0xffb40000 +#define SOCFPGA_CAN0_ADDRESS 0xffc00000 +#define SOCFPGA_CAN1_ADDRESS 0xffc01000 +#define SOCFPGA_UART0_ADDRESS 0xffc02000 +#define SOCFPGA_UART1_ADDRESS 0xffc03000 +#define SOCFPGA_I2C0_ADDRESS 0xffc04000 +#define SOCFPGA_I2C1_ADDRESS 0xffc05000 +#define SOCFPGA_I2C2_ADDRESS 0xffc06000 +#define SOCFPGA_I2C3_ADDRESS 0xffc07000 +#define SOCFPGA_SDR_ADDRESS 0xffc20000 +#define SOCFPGA_L4WD0_ADDRESS 0xffd02000 +#define SOCFPGA_L4WD1_ADDRESS 0xffd03000 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd08000 +#define SOCFPGA_SPIS0_ADDRESS 0xffe02000 +#define SOCFPGA_SPIS1_ADDRESS 0xffe03000 +#define SOCFPGA_SPIM0_ADDRESS 0xfff00000 +#define SOCFPGA_SPIM1_ADDRESS 0xfff01000 +#define SOCFPGA_SCANMGR_ADDRESS 0xfff02000 +#define SOCFPGA_ROM_ADDRESS 0xfffd0000 +#define SOCFPGA_MPUSCU_ADDRESS 0xfffec000 +#define SOCFPGA_MPUL2_ADDRESS 0xfffef000 +#define SOCFPGA_OCRAM_ADDRESS 0xffff0000 +#define SOCFPGA_LWFPGASLAVES_ADDRESS 0xff200000 +#define SOCFPGA_LWHPS2FPGAREGS_ADDRESS 0xff400000 +#define SOCFPGA_HPS2FPGAREGS_ADDRESS 0xff500000 +#define SOCFPGA_FPGA2HPSREGS_ADDRESS 0xff600000 +#define SOCFPGA_FPGAMGRREGS_ADDRESS 0xff706000 +#define SOCFPGA_ACPIDMAP_ADDRESS 0xff707000 +#define SOCFPGA_NANDDATA_ADDRESS 0xff900000 +#define SOCFPGA_QSPIDATA_ADDRESS 0xffa00000 +#define SOCFPGA_NANDREGS_ADDRESS 0xffb80000 +#define SOCFPGA_FPGAMGRDATA_ADDRESS 0xffb90000 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc08000 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc09000 +#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000 +#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd01000 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffe00000 +#define SOCFPGA_DMASECURE_ADDRESS 0xffe01000 + +#endif /* _SOCFPGA_BASE_ADDRS_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h new file mode 100644 index 0000000000..51d9815778 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2013 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYSTEM_MANAGER_H_ +#define _SYSTEM_MANAGER_H_ + +#ifndef __ASSEMBLY__ + +void sysmgr_pinmux_init(void); +void sysmgr_enable_warmrstcfgio(void); + +/* declaration for handoff table type */ +extern unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM]; + +#endif + +struct socfpga_system_manager { + /* System Manager Module */ + u32 siliconid1; /* 0x00 */ + u32 siliconid2; + u32 _pad_0x8_0xf[2]; + u32 wddbg; /* 0x10 */ + u32 bootinfo; + u32 hpsinfo; + u32 parityinj; + /* FPGA Interface Group */ + u32 fpgaintfgrp_gbl; /* 0x20 */ + u32 fpgaintfgrp_indiv; + u32 fpgaintfgrp_module; + u32 _pad_0x2c_0x2f; + /* Scan Manager Group */ + u32 scanmgrgrp_ctrl; /* 0x30 */ + u32 _pad_0x34_0x3f[3]; + /* Freeze Control Group */ + u32 frzctrl_vioctrl; /* 0x40 */ + u32 _pad_0x44_0x4f[3]; + u32 frzctrl_hioctrl; /* 0x50 */ + u32 frzctrl_src; + u32 frzctrl_hwctrl; + u32 _pad_0x5c_0x5f; + /* EMAC Group */ + u32 emacgrp_ctrl; /* 0x60 */ + u32 emacgrp_l3master; + u32 _pad_0x68_0x6f[2]; + /* DMA Controller Group */ + u32 dmagrp_ctrl; /* 0x70 */ + u32 dmagrp_persecurity; + u32 _pad_0x78_0x7f[2]; + /* Preloader (initial software) Group */ + u32 iswgrp_handoff[8]; /* 0x80 */ + u32 _pad_0xa0_0xbf[8]; /* 0xa0 */ + /* Boot ROM Code Register Group */ + u32 romcodegrp_ctrl; /* 0xc0 */ + u32 romcodegrp_cpu1startaddr; + u32 romcodegrp_initswstate; + u32 romcodegrp_initswlastld; + u32 romcodegrp_bootromswstate; /* 0xd0 */ + u32 __pad_0xd4_0xdf[3]; + /* Warm Boot from On-Chip RAM Group */ + u32 romcodegrp_warmramgrp_enable; /* 0xe0 */ + u32 romcodegrp_warmramgrp_datastart; + u32 romcodegrp_warmramgrp_length; + u32 romcodegrp_warmramgrp_execution; + u32 romcodegrp_warmramgrp_crc; /* 0xf0 */ + u32 __pad_0xf4_0xff[3]; + /* Boot ROM Hardware Register Group */ + u32 romhwgrp_ctrl; /* 0x100 */ + u32 _pad_0x104_0x107; + /* SDMMC Controller Group */ + u32 sdmmcgrp_ctrl; + u32 sdmmcgrp_l3master; + /* NAND Flash Controller Register Group */ + u32 nandgrp_bootstrap; /* 0x110 */ + u32 nandgrp_l3master; + /* USB Controller Group */ + u32 usbgrp_l3master; + u32 _pad_0x11c_0x13f[9]; + /* ECC Management Register Group */ + u32 eccgrp_l2; /* 0x140 */ + u32 eccgrp_ocram; + u32 eccgrp_usb0; + u32 eccgrp_usb1; + u32 eccgrp_emac0; /* 0x150 */ + u32 eccgrp_emac1; + u32 eccgrp_dma; + u32 eccgrp_can0; + u32 eccgrp_can1; /* 0x160 */ + u32 eccgrp_nand; + u32 eccgrp_qspi; + u32 eccgrp_sdmmc; + u32 _pad_0x170_0x3ff[164]; + /* Pin Mux Control Group */ + u32 emacio[20]; /* 0x400 */ + u32 flashio[12]; /* 0x450 */ + u32 generalio[28]; /* 0x480 */ + u32 _pad_0x4f0_0x4ff[4]; + u32 mixed1io[22]; /* 0x500 */ + u32 mixed2io[8]; /* 0x558 */ + u32 gplinmux[23]; /* 0x578 */ + u32 gplmux[71]; /* 0x5d4 */ + u32 nandusefpga; /* 0x6f0 */ + u32 _pad_0x6f4; + u32 rgmii1usefpga; /* 0x6f8 */ + u32 _pad_0x6fc_0x700[2]; + u32 i2c0usefpga; /* 0x704 */ + u32 sdmmcusefpga; /* 0x708 */ + u32 _pad_0x70c_0x710[2]; + u32 rgmii0usefpga; /* 0x714 */ + u32 _pad_0x718_0x720[3]; + u32 i2c3usefpga; /* 0x724 */ + u32 i2c2usefpga; /* 0x728 */ + u32 i2c1usefpga; /* 0x72c */ + u32 spim1usefpga; /* 0x730 */ + u32 _pad_0x734; + u32 spim0usefpga; /* 0x738 */ +}; + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX (1 << 0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO (1 << 1) +#define SYSMGR_ECC_OCRAM_EN (1 << 0) +#define SYSMGR_ECC_OCRAM_SERR (1 << 3) +#define SYSMGR_ECC_OCRAM_DERR (1 << 4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 +#define SYSMGR_FPGAINTF_SPIM0 (1 << 0) +#define SYSMGR_FPGAINTF_SPIM1 (1 << 1) +#define SYSMGR_FPGAINTF_EMAC0 (1 << 2) +#define SYSMGR_FPGAINTF_EMAC1 (1 << 3) +#define SYSMGR_FPGAINTF_NAND (1 << 4) +#define SYSMGR_FPGAINTF_SDMMC (1 << 5) + +/* FIXME: This is questionable macro. */ +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ + ((((drvsel) << 0) & 0x7) | (((smplsel) << 3) & 0x38)) + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#endif /* _SYSTEM_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/timer.h b/arch/arm/mach-socfpga/include/mach/timer.h new file mode 100644 index 0000000000..ee6969bac8 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/timer.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2012 Altera Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SOCFPGA_TIMER_H_ +#define _SOCFPGA_TIMER_H_ + +struct socfpga_timer { + u32 load_val; + u32 curr_val; + u32 ctrl; + u32 eoi; + u32 int_stat; +}; + +#endif -- cgit v1.2.1