From 28f40d4a4db2b6c701d349fd4fac286d21369de2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:40 +0900 Subject: ARM: uniphier: add PH1-Pro5 support The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/pinctrl/Makefile | 1 + arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c | 43 +++++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c (limited to 'arch/arm/mach-uniphier/pinctrl') diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index 542c670f97..a7852457f1 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -2,3 +2,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO5) += pinctrl-ph1-pro5.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c new file mode 100644 index 0000000000..a6cc0824e2 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro5.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_pro5_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */ + sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */ + sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */ + sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */ + sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */ + sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ + sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */ + sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */ + sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */ + sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */ + sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */ + sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */ + sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */ + sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */ + sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */ + sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */ +#endif + +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(124, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(125, 0, 4, 8); /* USB0OD -> USB0OD */ + sg_set_pinsel(126, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(127, 0, 4, 8); /* USB1OD -> USB1OD */ +#endif + + writel(1, SG_LOADPINCTRL); +} -- cgit v1.2.1