From a509161a21ef7584d614dc1530a2756dcfb217e0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 23 Mar 2015 00:07:32 +0900 Subject: ARM: UniPhier: disable L2 cache by lowlevel_init of U-Boot proper The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/late_lowlevel_init.S | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-uniphier/late_lowlevel_init.S') diff --git a/arch/arm/mach-uniphier/late_lowlevel_init.S b/arch/arm/mach-uniphier/late_lowlevel_init.S index 22be2a21da..1363364c80 100644 --- a/arch/arm/mach-uniphier/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/late_lowlevel_init.S @@ -6,7 +6,12 @@ */ #include +#include ENTRY(lowlevel_init) + ldr r1, = SSCC + ldr r0, [r1] + bic r0, r0, #SSCC_ON @ L2 disable + str r0, [r1] mov pc, lr ENDPROC(lowlevel_init) -- cgit v1.2.1