From 62118b7b0183d29755a101a6a5b88dee11c5f94b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 23 Mar 2015 00:07:31 +0900 Subject: ARM: UniPhier: optimize kicking secondary CPUs code Currently, the secondary CPU(s) are kicked three times: Boot ROM ---(kick)--> SPL ---(kick)--> U-boot ---(kick)--> Linux. It makes the boot sequence very complicated. This commit merges the first and the second kicks, so the secondary CPU(s) can directly jump from SPL to Linux. arch/arm/mach-uniphier/smp.S is no longer necessary. Linux boot test passed. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/cache_uniphier.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-uniphier/cache_uniphier.c') diff --git a/arch/arm/mach-uniphier/cache_uniphier.c b/arch/arm/mach-uniphier/cache_uniphier.c index 52f3c7c7a6..4bf01bce3e 100644 --- a/arch/arm/mach-uniphier/cache_uniphier.c +++ b/arch/arm/mach-uniphier/cache_uniphier.c @@ -1,6 +1,7 @@ /* * Copyright (C) 2012-2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2015 Socionext Inc. + * Author: Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,20 +120,10 @@ void v7_outer_cache_disable(void) writel(tmp, SSCC); } -void wakeup_secondary(void); - void enable_caches(void) { uint32_t reg; -#ifdef CONFIG_UNIPHIER_SMP - /* - * The secondary CPU must move to DDR, - * before L2 disable. - * On SPL, the Page Table is located on the L2. - */ - wakeup_secondary(); -#endif /* * UniPhier SoCs must use L2 cache for init stack pointer. * We disable L2 and L1 in this order. -- cgit v1.2.1