From aba11d4476b56eb7712184597eb303ae544f0c69 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 8 Sep 2015 11:38:03 +0200 Subject: ARM: tegra124: Clear IDDQ when enabling PLLC Enabling a PLL while IDDQ is high. The Linux kernel checks for this condition and warns about it verbosely, so while this seems to work fine, fix it up according to the programming guidelines provided in the Tegra K1 TRM (v02p), Section 5.3.8.1 ("PLLC and PLLC4 Startup Sequence"). Reported-by: Nicolas Chauvet Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra124/clock.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm/mach-tegra') diff --git a/arch/arm/mach-tegra/tegra124/clock.c b/arch/arm/mach-tegra/tegra124/clock.c index aa046e8950..1e71146236 100644 --- a/arch/arm/mach-tegra/tegra124/clock.c +++ b/arch/arm/mach-tegra/tegra124/clock.c @@ -809,6 +809,11 @@ void clock_early_init(void) tegra30_set_up_pllp(); + /* clear IDDQ before accessing any other PLLC registers */ + pllinfo = &tegra_pll_info_table[CLOCK_ID_CGENERAL]; + clrbits_le32(&clkrst->crc_pll[CLOCK_ID_CGENERAL].pll_misc, PLLC_IDDQ); + udelay(2); + /* * PLLC output frequency set to 600Mhz * PLLD output frequency set to 925Mhz -- cgit v1.2.1