From f9b814a8e99390d19628bc1b67c9567fc485d918 Mon Sep 17 00:00:00 2001 From: Sricharan R Date: Thu, 30 May 2013 03:19:34 +0000 Subject: ARM: DRA7xx: Correct the SYS_CLK to 20MHZ The sys_clk on the dra evm board is 20MHZ. Changing the configuration for the same. And also moving V_SCLK, V_OSCK defines to arch/clock.h for OMAP4+ boards. Signed-off-by: Sricharan R Signed-off-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap4/clock.h | 4 ++++ arch/arm/include/asm/arch-omap5/clock.h | 8 ++++++++ 2 files changed, 12 insertions(+) (limited to 'arch/arm/include/asm') diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index f544edfbd0..d7b61c298a 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -214,6 +214,10 @@ #define DPLL_NO_LOCK 0 #define DPLL_LOCK 1 +/* Clock Defines */ +#define V_OSCK 38400000 /* Clock output from T2 */ +#define V_SCLK V_OSCK + struct omap4_scrm_regs { u32 revision; /* 0x0000 */ u32 pad00[63]; diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 6d02835ead..86d4711a14 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -284,4 +284,12 @@ * into microsec and passing the value. */ #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219 + +#ifdef CONFIG_DRA7XX +#define V_OSCK 20000000 /* Clock output from T2 */ +#else +#define V_OSCK 19200000 /* Clock output from T2 */ +#endif + +#define V_SCLK V_OSCK #endif /* _CLOCKS_OMAP5_H_ */ -- cgit v1.2.1