From 97405d843ece2a53e67b801e02ee42005d26e172 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:38 +0000 Subject: ARM: DRA7xx: clocks: Update PLL values Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla Signed-off-by: Sricharan R --- arch/arm/include/asm/omap_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/include/asm/omap_common.h') diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index f33f28baf0..d5daa27d1e 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -29,7 +29,7 @@ #include -#define NUM_SYS_CLKS 8 +#define NUM_SYS_CLKS 7 struct prcm_regs { /* cm1.ckgen */ @@ -303,6 +303,7 @@ struct prcm_regs { /* l4 wkup regs */ u32 cm_abe_pll_ref_clksel; u32 cm_sys_clksel; + u32 cm_abe_pll_sys_clksel; u32 cm_wkup_clkstctrl; u32 cm_wkup_l4wkup_clkctrl; u32 cm_wkup_wdtimer1_clkctrl; -- cgit v1.2.1