From 148ba55cc618eaca19d7c86bdc003a7a71ee3a92 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 17 Jun 2013 14:37:01 +0200 Subject: zynq: Add new ddrc driver for ECC support The first 1MB is not initialized by first stage bootloader. Check if memory is setup to 16bit mode and ECC is enabled. If it is, clear the first 1MB. Also u-boot should report only the half size of memory. Acked-by: Jagannadha Sutradharudu Teki Signed-off-by: Michal Simek --- arch/arm/include/asm/arch-zynq/hardware.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm/include/asm/arch-zynq/hardware.h') diff --git a/arch/arm/include/asm/arch-zynq/hardware.h b/arch/arm/include/asm/arch-zynq/hardware.h index 25f0e3d9c7..ca56d8a2db 100644 --- a/arch/arm/include/asm/arch-zynq/hardware.h +++ b/arch/arm/include/asm/arch-zynq/hardware.h @@ -17,6 +17,7 @@ #define ZYNQ_SDHCI_BASEADDR1 0xE0101000 #define ZYNQ_I2C_BASEADDR0 0xE0004000 #define ZYNQ_I2C_BASEADDR1 0xE0005000 +#define ZYNQ_DDRC_BASEADDR 0xF8006000 /* Reflect slcr offsets */ struct slcr_regs { @@ -84,4 +85,11 @@ struct scu_regs { #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR) +struct ddrc_regs { + u32 ddrc_ctrl; /* 0x0 */ + u32 reserved[60]; + u32 ecc_scrub; /* 0xF4 */ +}; +#define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR) + #endif /* _ASM_ARCH_HARDWARE_H */ -- cgit v1.2.1