From ce0c474a72a72efe83808473a3411986a564e86b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 30 Jan 2016 16:37:55 -0700 Subject: tegra: video: Merge the two config structures together We have a structure for the display panel and another for the controller. There is some overlap between them. Merge them to simplify the driver. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra20/display.h | 39 ----------------------------- 1 file changed, 39 deletions(-) (limited to 'arch/arm/include/asm/arch-tegra20') diff --git a/arch/arm/include/asm/arch-tegra20/display.h b/arch/arm/include/asm/arch-tegra20/display.h index 35123edadc..3f5f9b1871 100644 --- a/arch/arm/include/asm/arch-tegra20/display.h +++ b/arch/arm/include/asm/arch-tegra20/display.h @@ -48,45 +48,6 @@ enum lcd_cache_t { FDT_LCD_CACHE_FLUSH, }; -/* Information about the display controller */ -struct fdt_disp_config { - int valid; /* config is valid */ - int width; /* width in pixels */ - int height; /* height in pixels */ - int bpp; /* number of bits per pixel */ - - /* - * log2 of number of bpp, in general, unless it bpp is 24 in which - * case this field holds 24 also! This is a U-Boot thing. - */ - int log2_bpp; - struct disp_ctlr *disp; /* Display controller to use */ - fdt_addr_t frame_buffer; /* Address of frame buffer */ - unsigned pixel_clock; /* Pixel clock in Hz */ - uint horiz_timing[FDT_LCD_TIMING_COUNT]; /* Horizontal timing */ - uint vert_timing[FDT_LCD_TIMING_COUNT]; /* Vertical timing */ - int panel_node; /* node offset of panel information */ -}; - -/* Information about the LCD panel */ -struct fdt_panel_config { - int pwm_channel; /* PWM channel to use for backlight */ - enum lcd_cache_t cache_type; - - struct gpio_desc backlight_en; /* GPIO for backlight enable */ - struct gpio_desc lvds_shutdown; /* GPIO for lvds shutdown */ - struct gpio_desc backlight_vdd; /* GPIO for backlight vdd */ - struct gpio_desc panel_vdd; /* GPIO for panel vdd */ - /* - * Panel required timings - * Timing 1: delay between panel_vdd-rise and data-rise - * Timing 2: delay between data-rise and backlight_vdd-rise - * Timing 3: delay between backlight_vdd and pwm-rise - * Timing 4: delay between pwm-rise and backlight_en-rise - */ - uint panel_timings[FDT_LCD_TIMINGS]; -}; - /** * Perform the next stage of the LCD init if it is time to do so. * -- cgit v1.2.1