From b40f734af9fdc47a0993f1f94f32d40a86f30587 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Mon, 1 Apr 2013 15:48:54 -0700 Subject: Tegra114: Initialize System Counter (TSC) with osc frequency T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren Reviewed-by: Stephen Warren --- arch/arm/include/asm/arch-tegra114/sysctr.h | 35 +++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra114/sysctr.h (limited to 'arch/arm/include/asm/arch-tegra114/sysctr.h') diff --git a/arch/arm/include/asm/arch-tegra114/sysctr.h b/arch/arm/include/asm/arch-tegra114/sysctr.h new file mode 100644 index 0000000000..c05e2c3281 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra114/sysctr.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _TEGRA114_SYSCTR_H_ +#define _TEGRA114_SYSCTR_H_ + +struct sysctr_ctlr { + u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */ + u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */ + u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */ + u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */ + u32 reserved1[4]; /* 0x10 - 0x1C */ + u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */ + u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */ + u32 reserved2[1002]; /* 0x28 - 0xFCC */ + u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */ +}; + +#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */ +#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */ + +#endif /* _TEGRA114_SYSCTR_H_ */ -- cgit v1.2.1