From 65530a842eeaf7ad07e0613ac6f883f2f1f1e33f Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Tue, 25 Sep 2012 20:21:13 +0000 Subject: tegra20: add clock_set_pllout function Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: Lucas Stach Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra/clock.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm/include/asm/arch-tegra/clock.h') diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index 3eff163e85..eac1dc2662 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -57,6 +57,18 @@ enum clock_osc_freq clock_get_osc_freq(void); unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn, u32 divp, u32 cpcon, u32 lfcon); +/** + * Set PLL output frequency + * + * @param clkid clock id + * @param pllout pll output id + * @param rate desired output rate + * + * @return 0 if ok, -1 on error (invalid clock id or no suitable divider) + */ +int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, + unsigned rate); + /** * Read low-level parameters of a PLL. * -- cgit v1.2.1