From 97405d843ece2a53e67b801e02ee42005d26e172 Mon Sep 17 00:00:00 2001 From: Lokesh Vutla Date: Thu, 30 May 2013 03:19:38 +0000 Subject: ARM: DRA7xx: clocks: Update PLL values Update PLL values. SYS_CLKSEL value for 20MHz is changed to 2. In other platforms SYS_CLKSEL value 2 represents reserved. But in sys_clk array ind 1 is used for 13Mhz. Since other platforms are not using 13Mhz, reusing index 1 for 20MHz. Signed-off-by: Lokesh Vutla Signed-off-by: Sricharan R --- arch/arm/include/asm/arch-omap4/clock.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/include/asm/arch-omap4/clock.h') diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h index d7b61c298a..d14d8fb8af 100644 --- a/arch/arm/include/asm/arch-omap4/clock.h +++ b/arch/arm/include/asm/arch-omap4/clock.h @@ -76,7 +76,7 @@ #define CM_CLKSEL_DCC_EN_MASK (1 << 22) /* CM_SYS_CLKSEL */ -#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 +#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7 /* CM_CLKSEL_CORE */ #define CLKSEL_CORE_SHIFT 0 -- cgit v1.2.1