From 9f3183d2d69f6d392fb943d249934f8648531e7e Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Mon, 26 Oct 2015 19:47:50 +0800 Subject: armv8/fsl_lsch3: Change arch to fsl-layerscape There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu Signed-off-by: Hou Zhiqiang Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- .../include/asm/arch-fsl-lsch3/ls2085a_stream_id.h | 64 ---------------------- 1 file changed, 64 deletions(-) delete mode 100644 arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h (limited to 'arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h') diff --git a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h b/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h deleted file mode 100644 index 5c945309a9..0000000000 --- a/arch/arm/include/asm/arch-fsl-lsch3/ls2085a_stream_id.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - * - */ -#ifndef __FSL_STREAM_ID_H -#define __FSL_STREAM_ID_H - -/* Stream IDs on ls2085a devices are not hardwired and are - * programmed by sw. There are a limited number of stream IDs - * available, and the partitioning of them is scenario dependent. - * This header defines the partitioning between legacy, PCI, - * and DPAA2 devices. - * - * This partitiong can be customized in this file depending - * on the specific hardware config-- e.g. perhaps not all - * PEX controllers are in use. - * - * On LS2085 stream IDs are programmed in AMQ registers (32-bits) for - * each of the different bus masters. The relationship between - * the AMQ registers and stream IDs is defined in the table below: - * AMQ bit streamID bit - * --------------------------- - * PL[18] 9 - * BMT[17] 8 - * VA[16] 7 - * [15] - - * ICID[14:7] - - * ICID[6:0] 6-0 - * ---------------------------- - */ - -#define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */ -#define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */ - -#define FSL_INVALID_STREAM_ID 0 - -#define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK) - -/* legacy devices */ -#define FSL_USB1_STREAM_ID 1 -#define FSL_USB2_STREAM_ID 2 -#define FSL_SDMMC_STREAM_ID 3 -#define FSL_SATA1_STREAM_ID 4 -#define FSL_SATA2_STREAM_ID 5 -#define FSL_DMA_STREAM_ID 6 - -/* PCI - programmed in PEXn_LUT by OS */ -/* 4 IDs per controller */ -#define FSL_PEX1_STREAM_ID_START 7 -#define FSL_PEX1_STREAM_ID_END 10 -#define FSL_PEX2_STREAM_ID_START 11 -#define FSL_PEX2_STREAM_ID_END 14 -#define FSL_PEX3_STREAM_ID_START 15 -#define FSL_PEX3_STREAM_ID_END 18 -#define FSL_PEX4_STREAM_ID_START 19 -#define FSL_PEX4_STREAM_ID_END 22 - -/* DPAA2 - set in MC DPC and alloced by MC */ -#define FSL_DPAA2_STREAM_ID_START 23 -#define FSL_DPAA2_STREAM_ID_END 63 - -#endif -- cgit v1.2.1