From 22b618346acb95dae8fddf151202829b6f78667f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 14 Jan 2015 19:28:38 +0100 Subject: sunxi: Drop pll6 setting from clock_init_uart As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c index d7a7040b72..e2a78676b1 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c @@ -45,10 +45,10 @@ void clock_init_safe(void) void clock_init_uart(void) { +#if CONFIG_CONS_INDEX < 5 struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; -#if CONFIG_CONS_INDEX < 5 /* uart clock source is apb2 */ writel(APB2_CLK_SRC_OSC24M| APB2_CLK_RATE_N_1| @@ -68,9 +68,6 @@ void clock_init_uart(void) /* enable R_PIO and R_UART clocks, and de-assert resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART); #endif - - /* Dup with clock_init_safe(), drop once sun6i SPL support lands */ - writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg); } int clock_twi_onoff(int port, int state) -- cgit v1.2.1 From dacc0881ac47660f8c5bc6ba6f6bbf2881f0364d Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 14 Jan 2015 19:56:33 +0100 Subject: sun9i: Add sun9i (A80) clock setup support Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- arch/arm/cpu/armv7/sunxi/Makefile | 1 + arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 68 ++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun9i.c (limited to 'arch/arm/cpu') diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 1720f7db01..1c4b7633f9 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o +obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o ifndef CONFIG_SPL_BUILD ifdef CONFIG_ARMV7_PSCI diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c new file mode 100644 index 0000000000..27179ba19c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c @@ -0,0 +1,68 @@ +/* + * sun9i specific clock code + * + * (C) Copyright 2015 Hans de Goede + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +void clock_init_uart(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* open the clock for uart */ + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + /* deassert uart reset */ + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + + CONFIG_CONS_INDEX - 1)); + + /* Dup with clock_init_safe(), drop once sun9i SPL support lands */ + writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg); +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 4) + return -1; + + /* set the apb reset and clock gate for twi */ + if (state) { + setbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + setbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + port)); + } else { + clrbits_le32(&ccm->apb1_reset_cfg, + 1 << (APB1_RESET_UART_SHIFT + port)); + clrbits_le32(&ccm->apb1_gate, + CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port)); + } + + return 0; +} + +unsigned int clock_get_pll4_periph0(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll4_periph0_cfg); + int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT); + int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT); + int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1; + const int k = 1; + + return ((24000000 * n * k) >> p) / m; +} -- cgit v1.2.1