From 074596c0b5f4e9a3642a3159a9fc7f8b8064c18a Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 7 Apr 2016 16:22:21 +0800 Subject: armv8/ls1043: Add workaround for DDR erratum A-008850 Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36 +++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 0cb010012e..0fb5c7f0cc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #ifdef CONFIG_CHAIN_OF_TRUST #include #endif @@ -271,6 +273,39 @@ static void erratum_a009660(void) #endif } +static void erratum_a008850_early(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 1 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + + /* disables propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + /* disable the re-ordering in DDRC */ + ddr_out32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); +#endif +} + +void erratum_a008850_post(void) +{ +#ifdef CONFIG_SYS_FSL_ERRATUM_A008850 + /* part 2 of 2 */ + struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + u32 tmp; + + /* enable propagation of barrier transactions to DDRC from CCI400 */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + /* enable the re-ordering in DDRC */ + tmp = ddr_in32(&ddr->eor); + tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS); + ddr_out32(&ddr->eor, tmp); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -295,6 +330,7 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ + erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); } -- cgit v1.2.1 From f13c99c2a265d0586702523fab56a3562de31f86 Mon Sep 17 00:00:00 2001 From: Alex Porosanu Date: Mon, 11 Apr 2016 10:42:50 +0300 Subject: armv8/fdt: add fixup_crypto_node For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 1e875c4b08..d17227ab2b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -20,6 +20,8 @@ #ifdef CONFIG_MP #include #endif +#include +#include int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -75,6 +77,23 @@ void ft_fixup_cpu(void *blob) void ft_cpu_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_LSCH2 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + unsigned int svr = in_be32(&gur->svr); + + /* delete crypto node if not on an E-processor */ + if (!IS_E_PROCESSOR(svr)) + fdt_fixup_crypto_node(blob, 0); +#if CONFIG_SYS_FSL_SEC_COMPAT >= 4 + else { + ccsr_sec_t __iomem *sec; + + sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); + } +#endif +#endif + #ifdef CONFIG_MP ft_fixup_cpu(blob); #endif -- cgit v1.2.1 From acb8f5e914814ac6c697edb86701958da251a223 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 22 Apr 2016 10:37:25 +0800 Subject: armv8: fsl-layerscape: Remove unnecessary flushing dcache As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d93990036b..9a5a6b53f7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -396,9 +396,6 @@ static inline void final_mmu_setup(void) flush_dcache_range((ulong)level0_table, (ulong)level0_table + gd->arch.tlb_size); -#ifdef CONFIG_SYS_DPAA_FMAN - flush_dcache_all(); -#endif /* point TTBR to the new table */ set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, MEMORY_ATTRIBUTES); -- cgit v1.2.1 From 1f49dc3e91c4d3a35fcddaf468bc1b615ced8a6b Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Wed, 27 Apr 2016 09:43:11 +0800 Subject: armv8: fsl-layerscape: spl: remove duplicate init_early_memctl_regs() init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index c1229c88af..4c8a9a0ba4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -48,9 +48,6 @@ void board_init_f(ulong dummy) memset((void *)gd, 0, sizeof(gd_t)); #ifdef CONFIG_LS2080A arch_cpu_init(); -#endif -#ifdef CONFIG_FSL_IFC - init_early_memctl_regs(); #endif board_early_init_f(); timer_init(); -- cgit v1.2.1 From f504227c9630edd7f05530b3f4dd99155ac58591 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Wed, 27 Apr 2016 09:45:23 +0800 Subject: armv8: fsl-layerscape: spl: fix the macro name of MMC mode MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-layerscape/spl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index 4c8a9a0ba4..5883c002be 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -29,7 +29,7 @@ u32 spl_boot_mode(void) switch (spl_boot_device()) { case BOOT_DEVICE_MMC1: #ifdef CONFIG_SPL_FAT_SUPPORT - return MMCSD_MODE_FAT; + return MMCSD_MODE_FS; #else return MMCSD_MODE_RAW; #endif -- cgit v1.2.1