From 07c6600068da31d0f7c67ac3eb92dfc4270f4c07 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 20 Mar 2015 19:28:10 -0700 Subject: armv8/fsl-lsch3: Set nodes in DVM domain This is required for TLB invalidation broadcasts to work. Signed-off-by: Scott Wood Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm/cpu/armv8/fsl-lsch3') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 53bdb4487c..018c61742e 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -15,6 +15,15 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ + /* Add fully-coherent masters to DVM domain */ + ldr x1, =CCI_MN_BASE + ldr x2, [x1, #CCI_MN_RNF_NODEID_LIST] + str x2, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] +1: ldr x3, [x1, #CCI_MN_DVM_DOMAIN_CTL_SET] + mvn x0, x3 + tst x0, x3 /* Wait for domain addition to complete */ + b.ne 1b + /* Set the SMMU page size in the sACR register */ ldr x1, =SMMU_BASE ldr w0, [x1, #0x10] -- cgit v1.2.1