From b940ca64b22ba8980fd4ec8dda028f6b1a2ed79d Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Mon, 23 Jun 2014 15:15:55 -0700 Subject: armv8/fsl-lsch3: Add support to load and start MC Firmware Adding support to load and start the Layerscape Management Complex (MC) firmware. First, the MC GCR register is set to 0 to reset all cores. MC firmware and DPL images are copied from their location in NOR flash to DDR. MC registers are updated with the location of these images. Deasserting the reset bit of MC GCR register releases core 0 to run. Core 1 will be released by MC firmware. Stop bits are not touched for this step. U-boot waits for MC until it boots up. In case of a failure, device tree is updated accordingly. The MC firmware image uses FIT format. Signed-off-by: J. German Rivera Signed-off-by: York Sun Signed-off-by: Lijun Pan Signed-off-by: Shruti Kanetkar --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 46965f08ad..c129d032f4 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -12,6 +12,7 @@ #include #include "cpu.h" #include "speed.h" +#include DECLARE_GLOBAL_DATA_PTR; @@ -423,3 +424,13 @@ int print_cpuinfo(void) return 0; } #endif + +int cpu_eth_init(bd_t *bis) +{ + int error = 0; + +#ifdef CONFIG_FSL_MC_ENET + error = mc_init(bis); +#endif + return error; +} -- cgit v1.2.1