From 6c747f4ad4eef87152f8d6de2169efe0a6a7a57f Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:11:22 -0800 Subject: armv8/fsl-lsch3: Change normal memory shareability According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 47b947f44f..ada1690ed9 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -150,7 +150,7 @@ static inline void final_mmu_setup(void) * set level 2 table 0 to cache-inhibit, covering 0 to 1GB */ section_l1t0 = 0; - section_l1t1 = BLOCK_SIZE_L0; + section_l1t1 = BLOCK_SIZE_L0 | PMD_SECT_OUTER_SHARE; section_l2 = 0; for (i = 0; i < 512; i++) { set_pgtable_section(level1_table_0, i, section_l1t0, @@ -168,10 +168,10 @@ static inline void final_mmu_setup(void) (u64)level2_table_0 | PMD_TYPE_TABLE; level1_table_0[2] = 0x80000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); level1_table_0[3] = 0xc0000000 | PMD_SECT_AF | PMD_TYPE_SECT | - PMD_ATTRINDX(MT_NORMAL); + PMD_SECT_OUTER_SHARE | PMD_ATTRINDX(MT_NORMAL); /* Rewrite table to enable cache */ set_pgtable_section(level2_table_0, -- cgit v1.2.1 From dcd468b8f43c5077c42c75b15cf3204e6b6be46c Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:42 -0800 Subject: armv8/fsl-lsch3: Convert flushing L3 to assembly to avoid using stack Flushing L3 cache in CCN-504 requries d-cache to be disabled. Using assembly function to guarantee stack is not used before flushing is completed. Timeout is needed for simualtor on which CCN-504 is not implemented. Return value can be checked for timeout situation. Change bootm.c to disable dcache instead of simply flushing, required by flushing L3. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 53 -------------------------------------- 1 file changed, 53 deletions(-) (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index ada1690ed9..2aaac017d2 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -242,59 +242,6 @@ int arch_cpu_init(void) return 0; } -/* - * flush_l3_cache - * Dickens L3 cache can be flushed by transitioning from FAM to SFONLY power - * state, by writing to HP-F P-state request register. - * Fixme: This function should moved to a common file if other SoCs also use - * the same Dickens. - */ -#define HNF0_PSTATE_REQ 0x04200010 -#define HNF1_PSTATE_REQ 0x04210010 -#define HNF2_PSTATE_REQ 0x04220010 -#define HNF3_PSTATE_REQ 0x04230010 -#define HNF4_PSTATE_REQ 0x04240010 -#define HNF5_PSTATE_REQ 0x04250010 -#define HNF6_PSTATE_REQ 0x04260010 -#define HNF7_PSTATE_REQ 0x04270010 -#define HNFPSTAT_MASK (0xFFFFFFFFFFFFFFFC) -#define HNFPSTAT_FAM 0x3 -#define HNFPSTAT_SFONLY 0x01 - -static void hnf_pstate_req(u64 *ptr, u64 state) -{ - int timeout = 1000; - out_le64(ptr, (in_le64(ptr) & HNFPSTAT_MASK) | (state & 0x3)); - ptr++; - /* checking if the transition is completed */ - while (timeout > 0) { - if (((in_le64(ptr) & 0x0c) >> 2) == (state & 0x3)) - break; - udelay(100); - timeout--; - } -} - -void flush_l3_cache(void) -{ - hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_SFONLY); - hnf_pstate_req((u64 *)HNF0_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF1_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF2_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF3_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF4_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF5_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF6_PSTATE_REQ, HNFPSTAT_FAM); - hnf_pstate_req((u64 *)HNF7_PSTATE_REQ, HNFPSTAT_FAM); -} - /* * This function is called from lib/board.c. * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. -- cgit v1.2.1 From b87e6f88e9218da3de371bb6cc8a34924153178e Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:49 -0800 Subject: armv8/fsl-lsch3: Add support for second DDR clock FSL-LSCH3 platforms can have multiple DDR clocks. LS2085A has one clock for general DDR controlers, and another clock for DP-DDR. DDR driver needs to change to support multiple clocks. Signed-off-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 2aaac017d2..42cee65546 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -367,6 +367,7 @@ int print_cpuinfo(void) printf("\n Bus: %-4s MHz ", strmhz(buf, sysinfo.freq_systembus)); printf("DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus)); + printf(" DP-DDR: %-4s MHz", strmhz(buf, sysinfo.freq_ddrbus2)); puts("\n"); return 0; -- cgit v1.2.1 From 7b3bd9a7988a8b4c8ba22a52b4927e8e59819b12 Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Tue, 6 Jan 2015 13:19:02 -0800 Subject: drivers/mc: Migrated MC Flibs to 0.5.2 Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera Signed-off-by: Lijun Pan Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/cpu/armv8/fsl-lsch3/cpu.c') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 42cee65546..49974878b9 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -10,10 +10,10 @@ #include #include #include +#include #include "cpu.h" #include "mp.h" #include "speed.h" -#include DECLARE_GLOBAL_DATA_PTR; -- cgit v1.2.1