From 3d90a2adcb1c240c9ef9e9088a4d49a40a3c9504 Mon Sep 17 00:00:00 2001 From: Lei Wen Date: Mon, 3 Oct 2011 20:33:41 +0000 Subject: ARM: pantheon: add mmc definition Signed-off-by: Lei Wen --- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm/cpu/arm926ejs/pantheon/cpu.c') diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index efc9395b96..db9b348ad3 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -42,6 +42,9 @@ int arch_cpu_init(void) struct panthmpmu_registers *mpmu = (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; + struct panthapmu_registers *apmu = + (struct panthapmu_registers *) PANTHEON_APMU_BASE; + /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ val = readl(&cpuregs->cpu_conf); val = val | SET_MRVL_ID; @@ -65,6 +68,14 @@ int arch_cpu_init(void) writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); #endif +#ifdef CONFIG_MV_SDHCI + /* Enable mmc clock */ + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd1); + writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, + &apmu->sd3); +#endif + icache_enable(); return 0; -- cgit v1.2.1