From c616a0df297e886f09bf88523bcd03a86bdf8704 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 9 Mar 2015 17:11:59 -0500 Subject: ARM: Introduce erratum workaround for 798870 Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- README | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'README') diff --git a/README b/README index 08283f52af..e918af73f9 100644 --- a/README +++ b/README @@ -690,6 +690,11 @@ The following options need to be configured: exists, unlike the similar options in the Linux kernel. Do not set these options unless they apply! + NOTE: The following can be machine specific errata. These + do have ability to provide rudimentary version and machine + specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_798870 + - Tegra SoC options: CONFIG_TEGRA_SUPPORT_NON_SECURE -- cgit v1.2.1