From 562f8df18da62ae02c4ace1e530451fe82c3312d Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 18 Jul 2014 06:07:21 +0200 Subject: spi: add config option to enable the WP pin function on st micron flashes enable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN Signed-off-by: Heiko Schocher Cc: Jagannadha Sutradharudu Teki --- README | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'README') diff --git a/README b/README index a35b92c889..37e4d1b09d 100644 --- a/README +++ b/README @@ -2930,6 +2930,17 @@ CBFS (Coreboot Filesystem) support memories can be connected with a given cs line. currently Xilinx Zynq qspi support these type of connections. + CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + enable the W#/Vpp signal to disable writing to the status + register on ST MICRON flashes like the N25Q128. + The status register write enable/disable bit, combined with + the W#/VPP signal provides hardware data protection for the + device as follows: When the enable/disable bit is set to 1, + and the W#/VPP signal is driven LOW, the status register + nonvolatile bits become read-only and the WRITE STATUS REGISTER + operation will not execute. The only way to exit this + hardware-protected mode is to drive W#/VPP HIGH. + - SystemACE Support: CONFIG_SYSTEMACE -- cgit v1.2.1