From f5f1f614bda83fae868d5634f86e0098162ceb3b Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 19 Nov 2013 11:02:15 +0530 Subject: mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes chip->ecc.hwctl() is used for preparing the H/W controller before read/write NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.) Though all ECC schemes in OMAP NAND driver use GPMC controller for generating ECC syndrome (for both Read/Write accesses). But but in current code HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this. This patch (1) removes omap_hwecc_init() and omap_hwecc_init_bch() as chip->ecc.hwctl will re-initializeGPMC before every read/write call. omap_hwecc_init_bch() -> omap_enable_ecc_bch() (2) merges the GPMC configuration code for all ECC schemes into single omap_enable_hwecc(), thus adding scalability for future ECC schemes. omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc() Signed-off-by: Pekon Gupta --- arch/arm/include/asm/omap_gpmc.h | 7 -- drivers/mtd/nand/omap_gpmc.c | 198 +++++++++++---------------------------- 2 files changed, 56 insertions(+), 149 deletions(-) diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index d4143ecd80..6ce5e65a8a 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -14,13 +14,6 @@ #define GPMC_BUF_EMPTY 0 #define GPMC_BUF_FULL 1 -#define ECCCLEAR (0x1 << 8) -#define ECCRESULTREG1 (0x1 << 0) -#define ECCSIZE512BYTE 0xFF -#define ECCSIZE1 (ECCSIZE512BYTE << 22) -#define ECCSIZE0 (ECCSIZE512BYTE << 12) -#define ECCSIZE0SEL (0x000 << 0) - /* Generic ECC Layouts */ /* Large Page x8 NAND device Layout */ #ifdef GPMC_NAND_ECC_LP_x8_LAYOUT diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 389c4de59a..48b2f75ed7 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -19,6 +19,8 @@ #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) static uint8_t cs; static __maybe_unused struct nand_ecclayout omap_ecclayout; @@ -60,21 +62,6 @@ int omap_spl_dev_ready(struct mtd_info *mtd) } #endif -/* - * omap_hwecc_init - Initialize the Hardware ECC for NAND flash in - * GPMC controller - * @mtd: MTD device structure - * - */ -static void __maybe_unused omap_hwecc_init(struct nand_chip *chip) -{ - /* - * Init ECC Control Register - * Clear all ECC | Enable Reg1 - */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, &gpmc_cfg->ecc_size_config); -} /* * gen_true_ecc - This function will generate true ECC value, which @@ -191,38 +178,6 @@ static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd, return 0; } -/* - * omap_enable_ecc - This function enables the hardware ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -static void __maybe_unused omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - uint32_t val, dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - - switch (mode) { - case NAND_ECC_READ: - case NAND_ECC_WRITE: - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - /* - * Size 0 = 0xFF, Size1 is 0xFF - both are 512 bytes - * tell all regs to generate size0 sized regs - * we just have a single ECC engine for all CS - */ - writel(ECCSIZE1 | ECCSIZE0 | ECCSIZE0SEL, - &gpmc_cfg->ecc_size_config); - val = (dev_width << 7) | (cs << 1) | (0x1); - writel(val, &gpmc_cfg->ecc_config); - break; - default: - printf("Error: Unrecognized Mode[%d]!\n", mode); - break; - } -} - /* * Generic BCH interface */ @@ -263,105 +218,65 @@ static __maybe_unused struct nand_bch_priv bch_priv = { }; /* - * omap_hwecc_init_bch - Initialize the BCH Hardware ECC for NAND flash in - * GPMC controller + * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write * @mtd: MTD device structure * @mode: Read/Write mode */ __maybe_unused -static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) +static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) { - uint32_t val; - uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; - uint32_t unused_length = 0; - uint32_t wr_mode = BCH_WRAPMODE_6; - struct nand_bch_priv *bch = chip->priv; - - /* Clear the ecc result registers, select ecc reg as 1 */ - writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); - - if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) { - wr_mode = BCH_WRAPMODE_1; - - switch (bch->nibbles) { - case ECC_BCH4_NIBBLES: - unused_length = 3; - break; - case ECC_BCH8_NIBBLES: - unused_length = 2; - break; - case ECC_BCH16_NIBBLES: - unused_length = 0; - break; - } - - /* - * This is ecc_size_config for ELM mode. Here we are using - * different settings for read and write access and also - * depending on BCH strength. - */ - switch (mode) { - case NAND_ECC_WRITE: - /* write access only setup eccsize1 config */ - val = ((unused_length + bch->nibbles) << 22); - break; - - case NAND_ECC_READ: - default: - /* - * by default eccsize0 selected for ecc1resultsize - * eccsize0 config. - */ - val = (bch->nibbles << 12); - /* eccsize1 config */ - val |= (unused_length << 22); - break; + struct nand_chip *nand = mtd->priv; + struct nand_bch_priv *bch = nand->priv; + unsigned int dev_width = (nand->options & NAND_BUSWIDTH_16) ? 1 : 0; + unsigned int ecc_algo = 0; + unsigned int bch_type = 0; + unsigned int eccsize1 = 0x00, eccsize0 = 0x00, bch_wrapmode = 0x00; + u32 ecc_size_config_val = 0; + u32 ecc_config_val = 0; + + /* configure GPMC for specific ecc-scheme */ + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_SW: + return; + case OMAP_ECC_HAM1_CODE_HW: + ecc_algo = 0x0; + bch_type = 0x0; + bch_wrapmode = 0x00; + eccsize0 = 0xFF; + eccsize1 = 0xFF; + break; + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + case OMAP_ECC_BCH8_CODE_HW: + ecc_algo = 0x1; + bch_type = 0x1; + if (mode == NAND_ECC_WRITE) { + bch_wrapmode = 0x01; + eccsize0 = 0; /* extra bits in nibbles per sector */ + eccsize1 = 28; /* OOB bits in nibbles per sector */ + } else { + bch_wrapmode = 0x01; + eccsize0 = 26; /* ECC bits in nibbles per sector */ + eccsize1 = 2; /* non-ECC bits in nibbles per sector */ } - } else { - /* - * This ecc_size_config setting is for BCH sw library. - * - * Note: we only support BCH8 currently with BCH sw library! - * Should be really easy to adobt to BCH4, however some omap3 - * have flaws with BCH4. - * - * Here we are using wrapping mode 6 both for reading and - * writing, with: - * size0 = 0 (no additional protected byte in spare area) - * size1 = 32 (skip 32 nibbles = 16 bytes per sector in - * spare area) - */ - val = (32 << 22) | (0 << 12); + break; + default: + return; } - /* ecc size configuration */ - writel(val, &gpmc_cfg->ecc_size_config); - - /* - * Configure the ecc engine in gpmc - * We assume 512 Byte sector pages for access to NAND. - */ - val = (1 << 16); /* enable BCH mode */ - val |= (bch->type << 12); /* setup BCH type */ - val |= (wr_mode << 8); /* setup wrapping mode */ - val |= (dev_width << 7); /* setup device width (16 or 8 bit) */ - val |= (cs << 1); /* setup chip select to work on */ - debug("set ECC_CONFIG=0x%08x\n", val); - writel(val, &gpmc_cfg->ecc_config); -} - -/* - * omap_enable_ecc_bch - This function enables the bch h/w ecc functionality - * @mtd: MTD device structure - * @mode: Read/Write mode - */ -__maybe_unused -static void omap_enable_ecc_bch(struct mtd_info *mtd, int32_t mode) -{ - struct nand_chip *chip = mtd->priv; - - omap_hwecc_init_bch(chip, mode); - /* enable ecc */ - writel((readl(&gpmc_cfg->ecc_config) | 0x1), &gpmc_cfg->ecc_config); + /* Clear ecc and enable bits */ + writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); + /* Configure ecc size for BCH */ + ecc_size_config_val = (eccsize1 << 22) | (eccsize0 << 12); + writel(ecc_size_config_val, &gpmc_cfg->ecc_size_config); + + /* Configure device details for BCH engine */ + ecc_config_val = ((ecc_algo << 16) | /* HAM1 | BCHx */ + (bch_type << 12) | /* BCH4/BCH8/BCH16 */ + (bch_wrapmode << 8) | /* wrap mode */ + (dev_width << 7) | /* bus width */ + (0x0 << 4) | /* number of sectors */ + (cs << 1) | /* ECC CS */ + (0x1)); /* enable ECC */ + writel(ecc_config_val, &gpmc_cfg->ecc_config); } /* @@ -835,7 +750,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 13; - nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch_sw; nand->ecc.calculate = omap_calculate_ecc_bch_sw; /* define ecc-layout */ @@ -852,7 +767,6 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - BADBLOCK_MARKER_LENGTH; - omap_hwecc_init_bch(nand, NAND_ECC_READ); bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; break; #else @@ -878,7 +792,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.strength = 8; nand->ecc.size = SECTOR_BYTES; nand->ecc.bytes = 14; - nand->ecc.hwctl = omap_enable_ecc_bch; + nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch; nand->ecc.calculate = omap_calculate_ecc_bch; nand->ecc.read_page = omap_read_page_bch; -- cgit v1.2.1 From 71a7f95600eeea03100af66e2f11498048f32cfe Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 19 Nov 2013 11:02:16 +0530 Subject: mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by processing the data passed during Read/Write accesses. All H/W based ECC schemes use GPMC controller to calculate ECC syndrome. But each BCHx_ECC scheme has its own implemetation of post-processing and fetching ECC syndrome from GPMC controller. This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way: - merges multiple chip->calculate API for different ECC schemes omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw() ==> omap_calculate_ecc() - removes omap_ecc_disable() and instead uses it as inline. Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 226 ++++++++++++------------------------------- 1 file changed, 63 insertions(+), 163 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 48b2f75ed7..ad5b0f17cc 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -21,7 +21,10 @@ #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) - +#ifdef CONFIG_BCH +static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, + 0x97, 0x79, 0xe5, 0x24, 0xb5}; +#endif static uint8_t cs; static __maybe_unused struct nand_ecclayout omap_ecclayout; @@ -142,42 +145,6 @@ static int __maybe_unused omap_correct_data(struct mtd_info *mtd, uint8_t *dat, return 0; } -/* - * omap_calculate_ecc - Generate non-inverted ECC bytes. - * - * Using noninverted ECC can be considered ugly since writing a blank - * page ie. padding will clear the ECC bytes. This is no problem as - * long nobody is trying to write data on the seemingly unused page. - * Reading an erased page will produce an ECC mismatch between - * generated and read ECC bytes that has to be dealt with separately. - * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC - * is used, the result of read will be 0x0 while the ECC offsets of the - * spare area will be 0xFF which will result in an ECC mismatch. - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer - */ -static int __maybe_unused omap_calculate_ecc(struct mtd_info *mtd, - const uint8_t *dat, uint8_t *ecc_code) -{ - u_int32_t val; - - /* Start Reading from HW ECC1_Result = 0x200 */ - val = readl(&gpmc_cfg->ecc1_result); - - ecc_code[0] = val & 0xFF; - ecc_code[1] = (val >> 16) & 0xFF; - ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - writel(0x000, &gpmc_cfg->ecc_config); - - return 0; -} - /* * Generic BCH interface */ @@ -194,12 +161,7 @@ struct nand_bch_priv { #define ECC_BCH8 1 #define ECC_BCH16 2 -/* GPMC ecc engine settings */ -#define BCH_WRAPMODE_1 1 /* BCH wrap mode 1 */ -#define BCH_WRAPMODE_6 6 /* BCH wrap mode 6 */ - /* BCH nibbles for diff bch levels */ -#define NAND_ECC_HW_BCH ((uint8_t)(NAND_ECC_HW_OOB_FIRST) + 1) #define ECC_BCH4_NIBBLES 13 #define ECC_BCH8_NIBBLES 26 #define ECC_BCH16_NIBBLES 52 @@ -211,7 +173,6 @@ struct nand_bch_priv { * When some users with other BCH strength will exists this have to change! */ static __maybe_unused struct nand_bch_priv bch_priv = { - .mode = NAND_ECC_HW_BCH, .type = ECC_BCH8, .nibbles = ECC_BCH8_NIBBLES, .control = NULL @@ -280,57 +241,76 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int32_t mode) } /* - * omap_ecc_disable - Disable H/W ECC calculation - * - * @mtd: MTD device structure - */ -static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) -{ - writel((readl(&gpmc_cfg->ecc_config) & ~0x1), &gpmc_cfg->ecc_config); -} - -/* - * BCH support using ELM module - */ -#ifdef CONFIG_NAND_OMAP_ELM -/* - * omap_read_bch8_result - Read BCH result for BCH8 level - * - * @mtd: MTD device structure - * @big_endian: When set read register 3 first - * @ecc_code: Read syndrome from BCH result registers + * omap_calculate_ecc - Read ECC result + * @mtd: MTD structure + * @dat: unused + * @ecc_code: ecc_code buffer + * Using noninverted ECC can be considered ugly since writing a blank + * page ie. padding will clear the ECC bytes. This is no problem as + * long nobody is trying to write data on the seemingly unused page. + * Reading an erased page will produce an ECC mismatch between + * generated and read ECC bytes that has to be dealt with separately. + * E.g. if page is 0xFF (fresh erased), and if HW ECC engine within GPMC + * is used, the result of read will be 0x0 while the ECC offsets of the + * spare area will be 0xFF which will result in an ECC mismatch. */ -static void omap_read_bch8_result(struct mtd_info *mtd, uint8_t big_endian, +static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, uint8_t *ecc_code) { - uint32_t *ptr; + struct nand_chip *chip = mtd->priv; + struct nand_bch_priv *bch = chip->priv; + uint32_t *ptr, val = 0; int8_t i = 0, j; - if (big_endian) { + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: + val = readl(&gpmc_cfg->ecc1_result); + ecc_code[0] = val & 0xFF; + ecc_code[1] = (val >> 16) & 0xFF; + ecc_code[2] = ((val >> 8) & 0x0F) | ((val >> 20) & 0xF0); + break; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: +#endif + case OMAP_ECC_BCH8_CODE_HW: ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[3]; - ecc_code[i++] = readl(ptr) & 0xFF; + val = readl(ptr); + ecc_code[i++] = (val >> 0) & 0xFF; ptr--; for (j = 0; j < 3; j++) { - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = readl(ptr) & 0xFF; + val = readl(ptr); + ecc_code[i++] = (val >> 24) & 0xFF; + ecc_code[i++] = (val >> 16) & 0xFF; + ecc_code[i++] = (val >> 8) & 0xFF; + ecc_code[i++] = (val >> 0) & 0xFF; ptr--; } - } else { - ptr = &gpmc_cfg->bch_result_0_3[0].bch_result_x[0]; - for (j = 0; j < 3; j++) { - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 8) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 16) & 0xFF; - ecc_code[i++] = (readl(ptr) >> 24) & 0xFF; - ptr++; - } - ecc_code[i++] = readl(ptr) & 0xFF; - ecc_code[i++] = 0; /* 14th byte is always zero */ + break; + default: + return -EINVAL; + } + /* ECC scheme specific syndrome customizations */ + switch (bch->ecc_scheme) { + case OMAP_ECC_HAM1_CODE_HW: + break; +#ifdef CONFIG_BCH + case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: + + for (i = 0; i < chip->ecc.bytes; i++) + *(ecc_code + i) = *(ecc_code + i) ^ + bch8_polynomial[i]; + break; +#endif + case OMAP_ECC_BCH8_CODE_HW: + ecc_code[chip->ecc.bytes - 1] = 0x00; + break; + default: + return -EINVAL; } + return 0; } +#ifdef CONFIG_NAND_OMAP_ELM /* * omap_rotate_ecc_bch - Rotate the syndrome bytes * @@ -366,35 +346,6 @@ static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, syndrome[i] = calc_ecc[j]; } -/* - * omap_calculate_ecc_bch - Read BCH ECC result - * - * @mtd: MTD structure - * @dat: unused - * @ecc_code: ecc_code buffer - */ -static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc_code) -{ - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t big_endian = 1; - int8_t ret = 0; - - if (bch->type == ECC_BCH8) - omap_read_bch8_result(mtd, big_endian, ecc_code); - else /* BCH4 and BCH16 currently not supported */ - ret = -1; - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - /* * omap_fix_errors_bch - Correct bch error in the data * @@ -551,57 +502,6 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, * OMAP3 BCH8 support (with BCH library) */ #ifdef CONFIG_BCH -/* - * omap_calculate_ecc_bch_sw - Read BCH ECC result - * - * @mtd: MTD device structure - * @dat: The pointer to data on which ecc is computed (unused here) - * @ecc: The ECC output buffer - */ -static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat, - uint8_t *ecc) -{ - int ret = 0; - size_t i; - unsigned long nsectors, val1, val2, val3, val4; - - nsectors = ((readl(&gpmc_cfg->ecc_config) >> 4) & 0x7) + 1; - - for (i = 0; i < nsectors; i++) { - /* Read hw-computed remainder */ - val1 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[0]); - val2 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[1]); - val3 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[2]); - val4 = readl(&gpmc_cfg->bch_result_0_3[i].bch_result_x[3]); - - /* - * Add constant polynomial to remainder, in order to get an ecc - * sequence of 0xFFs for a buffer filled with 0xFFs. - */ - *ecc++ = 0xef ^ (val4 & 0xFF); - *ecc++ = 0x51 ^ ((val3 >> 24) & 0xFF); - *ecc++ = 0x2e ^ ((val3 >> 16) & 0xFF); - *ecc++ = 0x09 ^ ((val3 >> 8) & 0xFF); - *ecc++ = 0xed ^ (val3 & 0xFF); - *ecc++ = 0x93 ^ ((val2 >> 24) & 0xFF); - *ecc++ = 0x9a ^ ((val2 >> 16) & 0xFF); - *ecc++ = 0xc2 ^ ((val2 >> 8) & 0xFF); - *ecc++ = 0x97 ^ (val2 & 0xFF); - *ecc++ = 0x79 ^ ((val1 >> 24) & 0xFF); - *ecc++ = 0xe5 ^ ((val1 >> 16) & 0xFF); - *ecc++ = 0x24 ^ ((val1 >> 8) & 0xFF); - *ecc++ = 0xb5 ^ (val1 & 0xFF); - } - - /* - * Stop reading anymore ECC vals and clear old results - * enable will be called if more reads are required - */ - omap_ecc_disable(mtd); - - return ret; -} - /** * omap_correct_data_bch_sw - Decode received data and correct errors * @mtd: MTD device structure @@ -752,7 +652,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.bytes = 13; nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch_sw; - nand->ecc.calculate = omap_calculate_ecc_bch_sw; + nand->ecc.calculate = omap_calculate_ecc; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; @@ -794,7 +694,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand, nand->ecc.bytes = 14; nand->ecc.hwctl = omap_enable_hwecc; nand->ecc.correct = omap_correct_data_bch; - nand->ecc.calculate = omap_calculate_ecc_bch; + nand->ecc.calculate = omap_calculate_ecc; nand->ecc.read_page = omap_read_page_bch; /* define ecc-layout */ ecclayout->eccbytes = nand->ecc.bytes * eccsteps; -- cgit v1.2.1 From 6e562b1106ea6afc78752f50925e87e9dd14f8b4 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 19 Nov 2013 11:02:17 +0530 Subject: mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes chip->ecc.correct() is used for detecting and correcting bit-flips during read operations. In omap-nand driver it implemented as: (a) omap_correct_data(): for h/w based ECC_HAM1 scheme (b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW for ECC_BCH8 scheme using GPMC and software lib/bch.c (c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW for ECC_BCH8 scheme using GPMC and ELM This patch updates (c) - checks for calc_ecc[]==0x00 so that error_correction is not required for known good pages. - adds scalability for other ECC_BCHx scheme by merging following omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch() - fixing logic for bit-flip correction based on error_loc[count] Signed-off-by: Pekon Gupta --- drivers/mtd/nand/omap_gpmc.c | 161 +++++++++++++++++++------------------------ 1 file changed, 71 insertions(+), 90 deletions(-) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index ad5b0f17cc..441b32144f 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -21,6 +21,9 @@ #define SECTOR_BYTES 512 #define ECCCLEAR (0x1 << 8) #define ECCRESULTREG1 (0x1 << 0) +/* 4 bit padding to make byte aligned, 56 = 52 + 4 */ +#define BCH4_BIT_PAD 4 + #ifdef CONFIG_BCH static u8 bch8_polynomial[] = {0xef, 0x51, 0x2e, 0x09, 0xed, 0x93, 0x9a, 0xc2, 0x97, 0x79, 0xe5, 0x24, 0xb5}; @@ -178,6 +181,23 @@ static __maybe_unused struct nand_bch_priv bch_priv = { .control = NULL }; +/* + * omap_reverse_list - re-orders list elements in reverse order [internal] + * @list: pointer to start of list + * @length: length of list +*/ +void omap_reverse_list(u8 *list, unsigned int length) +{ + unsigned int i, j; + unsigned int half_length = length / 2; + u8 tmp; + for (i = 0, j = length - 1; i < half_length; i++, j--) { + tmp = list[i]; + list[i] = list[j]; + list[j] = tmp; + } +} + /* * omap_enable_hwecc - configures GPMC as per ECC scheme before read/write * @mtd: MTD device structure @@ -311,77 +331,6 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, } #ifdef CONFIG_NAND_OMAP_ELM -/* - * omap_rotate_ecc_bch - Rotate the syndrome bytes - * - * @mtd: MTD device structure - * @calc_ecc: ECC read from ECC registers - * @syndrome: Rotated syndrome will be retuned in this array - * - */ -static void omap_rotate_ecc_bch(struct mtd_info *mtd, uint8_t *calc_ecc, - uint8_t *syndrome) -{ - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t n_bytes = 0; - int8_t i, j; - - switch (bch->type) { - case ECC_BCH4: - n_bytes = 8; - break; - - case ECC_BCH16: - n_bytes = 28; - break; - - case ECC_BCH8: - default: - n_bytes = 13; - break; - } - - for (i = 0, j = (n_bytes-1); i < n_bytes; i++, j--) - syndrome[i] = calc_ecc[j]; -} - -/* - * omap_fix_errors_bch - Correct bch error in the data - * - * @mtd: MTD device structure - * @data: Data read from flash - * @error_count:Number of errors in data - * @error_loc: Locations of errors in the data - * - */ -static void omap_fix_errors_bch(struct mtd_info *mtd, uint8_t *data, - uint32_t error_count, uint32_t *error_loc) -{ - struct nand_chip *chip = mtd->priv; - struct nand_bch_priv *bch = chip->priv; - uint8_t count = 0; - uint32_t error_byte_pos; - uint32_t error_bit_mask; - uint32_t last_bit = (bch->nibbles * 4) - 1; - - /* Flip all bits as specified by the error location array. */ - /* FOR( each found error location flip the bit ) */ - for (count = 0; count < error_count; count++) { - if (error_loc[count] > last_bit) { - /* Remove the ECC spare bits from correction. */ - error_loc[count] -= (last_bit + 1); - /* Offset bit in data region */ - error_byte_pos = ((512 * 8) - - (error_loc[count]) - 1) / 8; - /* Error Bit mask */ - error_bit_mask = 0x1 << (error_loc[count] % 8); - /* Toggle the error bit to make the correction. */ - data[error_byte_pos] ^= error_bit_mask; - } - } -} - /* * omap_correct_data_bch - Compares the ecc read from nand spare area * with ECC registers values and corrects one bit error if it has occured @@ -398,40 +347,72 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat, { struct nand_chip *chip = mtd->priv; struct nand_bch_priv *bch = chip->priv; - uint8_t syndrome[28]; - uint32_t error_count = 0; + uint32_t eccbytes = chip->ecc.bytes; + uint32_t error_count = 0, error_max; uint32_t error_loc[8]; - uint32_t i, ecc_flag; + uint32_t i, ecc_flag = 0; + uint8_t count, err = 0; + uint32_t byte_pos, bit_pos; + /* check calculated ecc */ + for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { + if (calc_ecc[i] != 0x00) + ecc_flag = 1; + } + if (!ecc_flag) + return 0; + + /* check for whether its a erased-page */ ecc_flag = 0; - for (i = 0; i < chip->ecc.bytes; i++) + for (i = 0; i < chip->ecc.bytes && !ecc_flag; i++) { if (read_ecc[i] != 0xff) ecc_flag = 1; - + } if (!ecc_flag) return 0; - elm_reset(); - elm_config((enum bch_level)(bch->type)); - /* * while reading ECC result we read it in big endian. * Hence while loading to ELM we have rotate to get the right endian. */ - omap_rotate_ecc_bch(mtd, calc_ecc, syndrome); - + switch (bch->ecc_scheme) { + case OMAP_ECC_BCH8_CODE_HW: + omap_reverse_list(calc_ecc, eccbytes - 1); + break; + default: + return -EINVAL; + } /* use elm module to check for errors */ - if (elm_check_error(syndrome, bch->nibbles, &error_count, - error_loc) != 0) { - printf("ECC: uncorrectable.\n"); - return -1; + elm_config((enum bch_level)(bch->type)); + if (elm_check_error(calc_ecc, bch->nibbles, &error_count, error_loc)) { + printf("nand: error: uncorrectable ECC errors\n"); + return -EINVAL; } - /* correct bch error */ - if (error_count > 0) - omap_fix_errors_bch(mtd, dat, error_count, error_loc); - - return 0; + for (count = 0; count < error_count; count++) { + switch (bch->type) { + case ECC_BCH8: + /* 14th byte in ECC is reserved to match ROM layout */ + error_max = SECTOR_BYTES + (eccbytes - 1); + break; + default: + return -EINVAL; + } + byte_pos = error_max - (error_loc[count] / 8) - 1; + bit_pos = error_loc[count] % 8; + if (byte_pos < SECTOR_BYTES) { + dat[byte_pos] ^= 1 << bit_pos; + printf("nand: bit-flip corrected @data=%d\n", byte_pos); + } else if (byte_pos < error_max) { + read_ecc[byte_pos - SECTOR_BYTES] = 1 << bit_pos; + printf("nand: bit-flip corrected @oob=%d\n", byte_pos - + SECTOR_BYTES); + } else { + err = -EBADMSG; + printf("nand: error: invalid bit-flip location\n"); + } + } + return (err) ? err : error_count; } /** -- cgit v1.2.1 From 32f4d729e775e707d3ef11ef320d83aaa1ef6afb Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Tue, 19 Nov 2013 11:02:18 +0530 Subject: board/ti/am335x/README: update for NAND boot NAND boot mode on AM335x EVM has been verified, and steps to use it has been documented and update in this README Signed-off-by: Pekon Gupta Acked-by: Peter Korsgaard Acked-by: Tom Rini --- board/ti/am335x/README | 53 ++++++++++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 17 deletions(-) diff --git a/board/ti/am335x/README b/board/ti/am335x/README index 2a30ab8981..947305b58d 100644 --- a/board/ti/am335x/README +++ b/board/ti/am335x/README @@ -46,23 +46,42 @@ NAND The AM335x GP EVM ships with a 256MiB NAND available in most profiles. In this example to program the NAND we assume that an SD card has been inserted with the files to write in the first SD slot and that mtdparts -have been configured correctly for the board. As a time saving measure we -load MLO into memory in one location, copy it into the three locatations -that the ROM checks for additional valid copies, then load U-Boot into -memory. We then write that whole section of memory to NAND. - -U-Boot # mmc rescan -U-Boot # env default -f -a -U-Boot # nand erase.chip -U-Boot # saveenv -U-Boot # load mmc 0 81000000 MLO -U-Boot # cp.b 81000000 81020000 20000 -U-Boot # cp.b 81000000 81040000 20000 -U-Boot # cp.b 81000000 81060000 20000 -U-Boot # load mmc 0 81080000 u-boot.img -U-Boot # nand write 81000000 0 260000 -U-Boot # load mmc 0 ${loadaddr} uImage -U-Boot # nand write ${loadaddr} kernel 500000 +have been configured correctly for the board. All images are first loaded +into memory, then written to NAND. + +Step-1: Building u-boot for NAND boot + Set following CONFIGxx options for NAND device. + CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page + CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page + CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block + CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) + +Step-2: Flashing NAND via MMC/SD + # select BOOTSEL to MMC/SD boot and boot from MMC/SD card + U-Boot # mmc rescan + # erase flash + U-Boot # nand erase.chip + U-Boot # env default -f -a + U-Boot # saveenv + # flash MLO. Redundant copies of MLO are kept for failsafe + U-Boot # load mmc 0 0x82000000 MLO + U-Boot # nand write 0x82000000 0x00000 0x20000 + U-Boot # nand write 0x82000000 0x20000 0x20000 + U-Boot # nand write 0x82000000 0x40000 0x20000 + U-Boot # nand write 0x82000000 0x60000 0x20000 + # flash u-boot.img + U-Boot # load mmc 0 0x82000000 u-boot.img + U-Boot # nand write 0x82000000 0x80000 0x60000 + # flash kernel image + U-Boot # load mmc 0 0x82000000 uImage + U-Boot # nand write 0x82000000 ${nandsrcaddr} ${nandimgsize} + # flash filesystem image + U-Boot # load mmc 0 0x82000000 filesystem.img + U-Boot # nand write 0x82000000 ${loadaddress} 0x300000 + +Step-3: Set BOOTSEL pin to select NAND boot, and POR the device. + The device should boot from images flashed on NAND device. NOR === -- cgit v1.2.1 From 50899183c933e31b1a43de1c4cc7a9085a417d96 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:26 +0530 Subject: mtd: nand: omap: remove redundant platform specific header: arch-xx/omap_gpmc.h Currently there are two sets of omap_gpmc.h header files (a) arch/arm/include/asm/omap_gpmc.h common header file for all platforms, containing defines and declarations used by GPMC NAND driver. (b) arch/arm/include/asm/arch-xx/omap_gpmc.h SoC platform specific header file containing defines like ECC layout. This patch removes platform specific arch-xx/omap_gpmc.c because: - GPMC hardware engine is common for all SoC platforms hence only (a) is enough - ECC layout is now defined in omap_nand.c driver itself based on ecc-scheme selected. Hence all ECC layout declarations in (b) are redundant. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- arch/arm/include/asm/arch-am33xx/omap_gpmc.h | 48 ---------------------------- arch/arm/include/asm/arch-omap3/mem.h | 10 ++++++ arch/arm/include/asm/arch-omap3/omap_gpmc.h | 36 --------------------- arch/arm/include/asm/omap_gpmc.h | 2 -- 4 files changed, 10 insertions(+), 86 deletions(-) delete mode 100644 arch/arm/include/asm/arch-am33xx/omap_gpmc.h delete mode 100644 arch/arm/include/asm/arch-omap3/omap_gpmc.h diff --git a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h b/arch/arm/include/asm/arch-am33xx/omap_gpmc.h deleted file mode 100644 index 00ad1d0672..0000000000 --- a/arch/arm/include/asm/arch-am33xx/omap_gpmc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines are based on AM33xx ELM */ -#define GPMC_NAND_HW_BCH4_ECC_LAYOUT {\ - .eccbytes = 32,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33},\ - .oobfree = {\ - {.offset = 34,\ - .length = 30 } } \ -} - -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57},\ - .oobfree = {\ - {.offset = 58,\ - .length = 6 } } \ -} - -#define GPMC_NAND_HW_BCH16_ECC_LAYOUT {\ - .eccbytes = 104,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,\ - 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,\ - 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,\ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,\ - 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,\ - 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,\ - 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,\ - 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,\ - 100, 101, 102, 103, 104, 105},\ - .oobfree = {\ - {.offset = 106,\ - .length = 8 } } \ -} -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index bcc22c43e1..18041913c4 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -419,6 +419,16 @@ enum { #define NET_GPMC_CONFIG6 0x00000FCF #define NET_GPMC_CONFIG7 0x00000f6c +/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ +#define NET_LAN9221_GPMC_CONFIG1 0x00001000 +#define NET_LAN9221_GPMC_CONFIG2 0x00060700 +#define NET_LAN9221_GPMC_CONFIG3 0x00020201 +#define NET_LAN9221_GPMC_CONFIG4 0x06000700 +#define NET_LAN9221_GPMC_CONFIG5 0x0006090A +#define NET_LAN9221_GPMC_CONFIG6 0x87030000 +#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c + + /* max number of GPMC Chip Selects */ #define GPMC_MAX_CS 8 /* max number of GPMC regs */ diff --git a/arch/arm/include/asm/arch-omap3/omap_gpmc.h b/arch/arm/include/asm/arch-omap3/omap_gpmc.h deleted file mode 100644 index bf2321932a..0000000000 --- a/arch/arm/include/asm/arch-omap3/omap_gpmc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_OMAP_GPMC_H -#define __ASM_ARCH_OMAP_GPMC_H - -/* - * These GPMC_NAND_HW_BCHx_ECC_LAYOUT defines using the BCH library. - * The OOB layout was first defined by linx kernel in commit - * 0e618ef0a6a33cf7ef96c2c824402088dd8ef48c, we have to reuse it here cause - * we want to be compatible. - */ -#define GPMC_NAND_HW_BCH8_ECC_LAYOUT {\ - .eccbytes = 56,\ - .eccpos = {12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22,\ - 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,\ - 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,\ - 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63},\ - .oobfree = {\ - {.offset = 2,\ - .length = 10 } } \ -} - -/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ -#define NET_LAN9221_GPMC_CONFIG1 0x00001000 -#define NET_LAN9221_GPMC_CONFIG2 0x00060700 -#define NET_LAN9221_GPMC_CONFIG3 0x00020201 -#define NET_LAN9221_GPMC_CONFIG4 0x06000700 -#define NET_LAN9221_GPMC_CONFIG5 0x0006090A -#define NET_LAN9221_GPMC_CONFIG6 0x87030000 -#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c - -#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index 6ce5e65a8a..5250109a5b 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -9,8 +9,6 @@ #ifndef __ASM_OMAP_GPMC_H #define __ASM_OMAP_GPMC_H -#include - #define GPMC_BUF_EMPTY 0 #define GPMC_BUF_FULL 1 -- cgit v1.2.1 From a7e36fc95fa2c915bb95e845c8945ca926575f5b Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:27 +0530 Subject: mtd: nand: omap: remove unused #defines from common omap_gpmc.h OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI params or nand_id[] table. And based on that it defines ECC layout. This patch 1) removes following board configs used for defining NAND ECC layout - GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND) - GPMC_NAND_ECC_LP_x8_LAYOUT (for large page x8 NAND) - GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND) - GPMC_NAND_ECC_SP_x8_LAYOUT (for small page x8 NAND) 2) removes unused #defines in common omap_gpmc.h depending on above configs Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- arch/arm/include/asm/omap_gpmc.h | 47 ---------------------------------- include/configs/am335x_evm.h | 1 - include/configs/am335x_igep0033.h | 1 - include/configs/am3517_crane.h | 1 - include/configs/am3517_evm.h | 1 - include/configs/cm_t35.h | 2 -- include/configs/devkit8000.h | 2 -- include/configs/dig297.h | 2 -- include/configs/mcx.h | 1 - include/configs/omap3_beagle.h | 2 -- include/configs/omap3_evm_common.h | 1 - include/configs/omap3_igep00x0.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omap3_overo.h | 2 -- include/configs/omap3_pandora.h | 2 -- include/configs/omap3_zoom1.h | 2 -- include/configs/siemens-am33x-common.h | 1 - include/configs/tam3517-common.h | 1 - include/configs/tricorder.h | 2 -- 19 files changed, 73 deletions(-) diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index 5250109a5b..3caaed85fb 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -12,53 +12,6 @@ #define GPMC_BUF_EMPTY 0 #define GPMC_BUF_FULL 1 -/* Generic ECC Layouts */ -/* Large Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ - 9, 10, 11, 12},\ - .oobfree = {\ - {.offset = 13,\ - .length = 51 } } \ -} -#endif - -/* Large Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 12,\ - .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13},\ - .oobfree = {\ - {.offset = 14,\ - .length = 50 } } \ -} -#endif - -/* Small Page x8 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {1, 2, 3},\ - .oobfree = {\ - {.offset = 4,\ - .length = 12 } } \ -} -#endif - -/* Small Page x16 NAND device Layout */ -#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT -#define GPMC_NAND_HW_ECC_LAYOUT {\ - .eccbytes = 3,\ - .eccpos = {2, 3, 4},\ - .oobfree = {\ - {.offset = 5,\ - .length = 11 } } \ -} -#endif - enum omap_ecc { /* 1-bit ECC calculation by Software, Error detection by Software */ OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 59a8f36d16..a5736b7f0a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -404,7 +404,6 @@ /* NAND support */ #ifdef CONFIG_NAND #define CONFIG_CMD_NAND -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) #define MTDIDS_DEFAULT "nand0=omap2-nand.0" #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ diff --git a/include/configs/am335x_igep0033.h b/include/configs/am335x_igep0033.h index 115d1b37c9..c00d54f7b2 100644 --- a/include/configs/am335x_igep0033.h +++ b/include/configs/am335x_igep0033.h @@ -188,7 +188,6 @@ #define CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* phys address CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ONFI_DETECTION 1 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 468fb43ea8..4407b454dd 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -268,7 +268,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index b8b99c806f..0102ff5b7f 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -277,7 +277,6 @@ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 08c67f588c..cfc4f9bb8e 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -156,8 +156,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x8_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 4f43ba9882..16a00ebe86 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -116,8 +116,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 5049afca7a..af6f56bb34 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -143,8 +143,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ #if defined(CONFIG_CMD_NET) diff --git a/include/configs/mcx.h b/include/configs/mcx.h index 7c5c2f4d1c..47244c0034 100644 --- a/include/configs/mcx.h +++ b/include/configs/mcx.h @@ -321,7 +321,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index c58bc91a50..ac0ed4371c 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -183,8 +183,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_evm_common.h b/include/configs/omap3_evm_common.h index 43616e2b02..7f3424b4f0 100644 --- a/include/configs/omap3_evm_common.h +++ b/include/configs/omap3_evm_common.h @@ -208,7 +208,6 @@ #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #elif defined(CONFIG_CMD_ONENAND) #define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 20fbbecdfb..12d8141e22 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -154,7 +154,6 @@ #ifdef CONFIG_NAND #define PISMO1_NAND_SIZE GPMC_SIZE_128M /* Configure the PISMO */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE (512 << 10) /* Total Size Environment */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index bedd6f9cb3..0d03c75ce3 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -295,7 +295,6 @@ #if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #endif diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index e0f026269f..007e27f9f1 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -119,8 +119,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index eacdfaaa53..da67787e69 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -131,8 +131,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 1dd53fa133..f0fa96efcb 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,8 +138,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_JFFS2_NAND diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index 286304295d..98b6e7206d 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -457,7 +457,6 @@ #define CONFIG_NAND_OMAP_GPMC #define CONFIG_NAND_OMAP_ELM -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h index d44b5c036d..3522c1a07a 100644 --- a/include/configs/tam3517-common.h +++ b/include/configs/tam3517-common.h @@ -186,7 +186,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define CONFIG_NAND_OMAP_GPMC -#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_ENV_IS_IN_NAND #define SMNAND_ENV_OFFSET 0x180000 /* environment starts here */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index cc4001fcd1..62f97d24fb 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -134,8 +134,6 @@ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 - #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ #define CONFIG_BCH -- cgit v1.2.1 From 51d192c40daa2b58cfc96c772799d9c632df33e3 Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:28 +0530 Subject: mtd: nand: omap: merge duplicate GPMC data from different arch-xx headers into common omap_gpmc.h Each SoC platform (AM33xx, OMAP3, OMAP4, OMAP5) has its own copy of GPMC related defines and declarations scattered in SoC platform specific header files like include/asm/arch-xx/cpu.h However, GPMC hardware remains same across all platforms thus this patch merges GPMC data scattered across different arch-xx specific header files into single header file include/asm/arch/omap_gpmc.h Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- arch/arm/include/asm/arch-am33xx/cpu.h | 51 -------------------------- arch/arm/include/asm/arch-am33xx/sys_proto.h | 1 + arch/arm/include/asm/arch-omap3/cpu.h | 54 +--------------------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + arch/arm/include/asm/arch-omap4/cpu.h | 45 ----------------------- arch/arm/include/asm/arch-omap4/sys_proto.h | 1 + arch/arm/include/asm/arch-omap5/cpu.h | 45 ----------------------- arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_gpmc.h | 53 +++++++++++++++++++++++++++ drivers/mtd/nand/omap_elm.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 1 - 11 files changed, 59 insertions(+), 196 deletions(-) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 71bed4efab..d9f0306b0a 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -78,58 +78,7 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[12]; /* 0x224 */ - u32 testmomde_ctrl; /* 0x230 */ - u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ -}; -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; #ifndef CONFIG_AM43XX /* Encapsulating core pll registers */ diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 2e5c356e44..f73e285a89 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,6 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include #include #define BOARD_REV_ID 0x0 diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index 61ec8f24e0..4d06ef83fe 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -77,59 +77,7 @@ struct ctrl_id { #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) #ifndef __KERNEL_STRICT_NAMES -#ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[0x1C]; /* fill up to 0x240 */ - struct bch_res_0_3 bch_result_0_3[7]; /* 0x240 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - -#else /* __ASSEMBLY__ */ +#ifdef __ASSEMBLY__ #define GPMC_CONFIG1 0x00 #define GPMC_CONFIG2 0x04 #define GPMC_CONFIG3 0x08 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 43b54f7cae..83d7f1146f 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -7,6 +7,7 @@ */ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ +#include typedef struct { u32 mtype; diff --git a/arch/arm/include/asm/arch-omap4/cpu.h b/arch/arm/include/asm/arch-omap4/cpu.h index 545d9d96ad..c21fb54714 100644 --- a/arch/arm/include/asm/arch-omap4/cpu.h +++ b/arch/arm/include/asm/arch-omap4/cpu.h @@ -14,51 +14,6 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res[0xc]; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index fc9472544d..ea8b72c431 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -12,6 +12,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h index fb5a568b69..5f1d7454d0 100644 --- a/arch/arm/include/asm/arch-omap5/cpu.h +++ b/arch/arm/include/asm/arch-omap5/cpu.h @@ -16,51 +16,6 @@ #ifndef __KERNEL_STRICT_NAMES #ifndef __ASSEMBLY__ -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - struct gptimer { u32 tidr; /* 0x00 r */ u8 res1[0xc]; diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 43011a4acd..4247473a66 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -12,6 +12,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h index 3caaed85fb..22f6573969 100644 --- a/arch/arm/include/asm/omap_gpmc.h +++ b/arch/arm/include/asm/omap_gpmc.h @@ -28,4 +28,57 @@ enum omap_ecc { OMAP_ECC_BCH8_CODE_HW, }; +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ + u8 res7[12]; /* 0x224 */ + u32 testmomde_ctrl; /* 0x230 */ + u8 res8[12]; /* 0x234 */ + struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + #endif /* __ASM_OMAP_GPMC_H */ diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 2aa7807f3e..64dca4fe98 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -16,9 +16,9 @@ #include #include #include -#include #include #include +#include #define ELM_DEFAULT_POLY (0) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 441b32144f..b54e39e1cd 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include -- cgit v1.2.1 From 6aff05098864233caf9d24cb020e67b00ada4e3e Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:29 +0530 Subject: mtd: nand: omap: move omap_gpmc.h from arch/arm/include/asm to drivers/mtd/nand omap_gpmc.h is a generic header used by OMAP NAND driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- arch/arm/include/asm/arch-am33xx/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap3/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap4/sys_proto.h | 2 +- arch/arm/include/asm/arch-omap5/sys_proto.h | 2 +- arch/arm/include/asm/omap_gpmc.h | 84 ---------------------------- board/isee/igep00x0/igep00x0.c | 1 - board/overo/overo.c | 1 - drivers/mtd/nand/omap_elm.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/linux/mtd/omap_gpmc.h | 84 ++++++++++++++++++++++++++++ 10 files changed, 90 insertions(+), 92 deletions(-) delete mode 100644 arch/arm/include/asm/omap_gpmc.h create mode 100644 include/linux/mtd/omap_gpmc.h diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index f73e285a89..91ff2ad0e4 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -10,7 +10,7 @@ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#include +#include #include #define BOARD_REV_ID 0x0 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 83d7f1146f..44fa66f8a3 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -7,7 +7,7 @@ */ #ifndef _SYS_PROTO_H_ #define _SYS_PROTO_H_ -#include +#include typedef struct { u32 mtype; diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h index ea8b72c431..b338a1566c 100644 --- a/arch/arm/include/asm/arch-omap4/sys_proto.h +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 4247473a66..9e007c87ae 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/arm/include/asm/omap_gpmc.h b/arch/arm/include/asm/omap_gpmc.h deleted file mode 100644 index 22f6573969..0000000000 --- a/arch/arm/include/asm/omap_gpmc.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * (C) Copyright 2004-2008 Texas Instruments, - * Rohit Choraria - * - * (C) Copyright 2013 Andreas Bießmann - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_OMAP_GPMC_H -#define __ASM_OMAP_GPMC_H - -#define GPMC_BUF_EMPTY 0 -#define GPMC_BUF_FULL 1 - -enum omap_ecc { - /* 1-bit ECC calculation by Software, Error detection by Software */ - OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ - /* 1-bit ECC calculation by GPMC, Error detection by Software */ - /* ECC layout compatible to legacy ROMCODE. */ - OMAP_ECC_HAM1_CODE_HW, - /* 4-bit ECC calculation by GPMC, Error detection by Software */ - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, - /* 4-bit ECC calculation by GPMC, Error detection by ELM */ - OMAP_ECC_BCH4_CODE_HW, - /* 8-bit ECC calculation by GPMC, Error detection by Software */ - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, - /* 8-bit ECC calculation by GPMC, Error detection by ELM */ - OMAP_ECC_BCH8_CODE_HW, -}; - -struct gpmc_cs { - u32 config1; /* 0x00 */ - u32 config2; /* 0x04 */ - u32 config3; /* 0x08 */ - u32 config4; /* 0x0C */ - u32 config5; /* 0x10 */ - u32 config6; /* 0x14 */ - u32 config7; /* 0x18 */ - u32 nand_cmd; /* 0x1C */ - u32 nand_adr; /* 0x20 */ - u32 nand_dat; /* 0x24 */ - u8 res[8]; /* blow up to 0x30 byte */ -}; - -struct bch_res_0_3 { - u32 bch_result_x[4]; -}; - -struct gpmc { - u8 res1[0x10]; - u32 sysconfig; /* 0x10 */ - u8 res2[0x4]; - u32 irqstatus; /* 0x18 */ - u32 irqenable; /* 0x1C */ - u8 res3[0x20]; - u32 timeout_control; /* 0x40 */ - u8 res4[0xC]; - u32 config; /* 0x50 */ - u32 status; /* 0x54 */ - u8 res5[0x8]; /* 0x58 */ - struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x14]; /* 0x1E0 */ - u32 ecc_config; /* 0x1F4 */ - u32 ecc_control; /* 0x1F8 */ - u32 ecc_size_config; /* 0x1FC */ - u32 ecc1_result; /* 0x200 */ - u32 ecc2_result; /* 0x204 */ - u32 ecc3_result; /* 0x208 */ - u32 ecc4_result; /* 0x20C */ - u32 ecc5_result; /* 0x210 */ - u32 ecc6_result; /* 0x214 */ - u32 ecc7_result; /* 0x218 */ - u32 ecc8_result; /* 0x21C */ - u32 ecc9_result; /* 0x220 */ - u8 res7[12]; /* 0x224 */ - u32 testmomde_ctrl; /* 0x230 */ - u8 res8[12]; /* 0x234 */ - struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ -}; - -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - -#endif /* __ASM_OMAP_GPMC_H */ diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 7a7500b342..3b2b1f15b8 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/board/overo/overo.c b/board/overo/overo.c index 9ac35d2f4e..1192d02e91 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include "overo.h" diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 64dca4fe98..55a631deb4 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -16,7 +16,7 @@ #include #include #include -#include +#include #include #include diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index b54e39e1cd..452e40f04e 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/linux/mtd/omap_gpmc.h b/include/linux/mtd/omap_gpmc.h new file mode 100644 index 0000000000..22f6573969 --- /dev/null +++ b/include/linux/mtd/omap_gpmc.h @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, + * Rohit Choraria + * + * (C) Copyright 2013 Andreas Bießmann + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_OMAP_GPMC_H +#define __ASM_OMAP_GPMC_H + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +enum omap_ecc { + /* 1-bit ECC calculation by Software, Error detection by Software */ + OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ + /* 1-bit ECC calculation by GPMC, Error detection by Software */ + /* ECC layout compatible to legacy ROMCODE. */ + OMAP_ECC_HAM1_CODE_HW, + /* 4-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW, + /* 4-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH4_CODE_HW, + /* 8-bit ECC calculation by GPMC, Error detection by Software */ + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW, + /* 8-bit ECC calculation by GPMC, Error detection by ELM */ + OMAP_ECC_BCH8_CODE_HW, +}; + +struct gpmc_cs { + u32 config1; /* 0x00 */ + u32 config2; /* 0x04 */ + u32 config3; /* 0x08 */ + u32 config4; /* 0x0C */ + u32 config5; /* 0x10 */ + u32 config6; /* 0x14 */ + u32 config7; /* 0x18 */ + u32 nand_cmd; /* 0x1C */ + u32 nand_adr; /* 0x20 */ + u32 nand_dat; /* 0x24 */ + u8 res[8]; /* blow up to 0x30 byte */ +}; + +struct bch_res_0_3 { + u32 bch_result_x[4]; +}; + +struct gpmc { + u8 res1[0x10]; + u32 sysconfig; /* 0x10 */ + u8 res2[0x4]; + u32 irqstatus; /* 0x18 */ + u32 irqenable; /* 0x1C */ + u8 res3[0x20]; + u32 timeout_control; /* 0x40 */ + u8 res4[0xC]; + u32 config; /* 0x50 */ + u32 status; /* 0x54 */ + u8 res5[0x8]; /* 0x58 */ + struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ + u8 res6[0x14]; /* 0x1E0 */ + u32 ecc_config; /* 0x1F4 */ + u32 ecc_control; /* 0x1F8 */ + u32 ecc_size_config; /* 0x1FC */ + u32 ecc1_result; /* 0x200 */ + u32 ecc2_result; /* 0x204 */ + u32 ecc3_result; /* 0x208 */ + u32 ecc4_result; /* 0x20C */ + u32 ecc5_result; /* 0x210 */ + u32 ecc6_result; /* 0x214 */ + u32 ecc7_result; /* 0x218 */ + u32 ecc8_result; /* 0x21C */ + u32 ecc9_result; /* 0x220 */ + u8 res7[12]; /* 0x224 */ + u32 testmomde_ctrl; /* 0x230 */ + u8 res8[12]; /* 0x234 */ + struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ +}; + +/* Used for board specific gpmc initialization */ +extern struct gpmc *gpmc_cfg; + +#endif /* __ASM_OMAP_GPMC_H */ -- cgit v1.2.1 From 2eda892f00fbcf46143326f72e8ac5b472bd225a Mon Sep 17 00:00:00 2001 From: pekon gupta Date: Fri, 22 Nov 2013 16:53:30 +0530 Subject: mtd: nand: omap: move omap_elm.h from arch/arm/include/asm to drivers/mtd/nand omap_elm.h is a generic header used by OMAP ELM driver for all TI platfoms. Hence this file should be present in generic folder instead of architecture specific include folder. Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta --- arch/arm/include/asm/omap_elm.h | 77 ----------------------------------------- drivers/mtd/nand/omap_elm.c | 2 +- drivers/mtd/nand/omap_gpmc.c | 2 +- include/linux/mtd/omap_elm.h | 77 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 79 deletions(-) delete mode 100644 arch/arm/include/asm/omap_elm.h create mode 100644 include/linux/mtd/omap_elm.h diff --git a/arch/arm/include/asm/omap_elm.h b/arch/arm/include/asm/omap_elm.h deleted file mode 100644 index 45454eaf0f..0000000000 --- a/arch/arm/include/asm/omap_elm.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2010-2011 Texas Instruments, - * Mansoor Ahamed - * - * Derived from work done by Rohit Choraria for omap3 - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_ELM_H -#define __ASM_ARCH_ELM_H -/* - * ELM Module Registers - */ - -/* ELM registers bit fields */ -#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) -#define ELM_SYSCONFIG_SOFTRESET (0x2) -#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) -#define ELM_SYSSTATUS_RESETDONE (0x1) -#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) -#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) -#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) -#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) -#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) -#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) - -#ifndef __ASSEMBLY__ - -enum bch_level { - BCH_4_BIT = 0, - BCH_8_BIT, - BCH_16_BIT -}; - - -/* BCH syndrome registers */ -struct syndrome { - u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ - u8 res1[36]; /* 0x41c */ -}; - -/* BCH error status & location register */ -struct location { - u32 location_status; /* 0x800 */ - u8 res1[124]; /* 0x804 */ - u32 error_location_x[16]; /* 0x880.... */ - u8 res2[64]; /* 0x8c0 */ -}; - -/* BCH ELM register map - do not try to allocate memmory for this structure. - * We have used plenty of reserved variables to fill the slots in the ELM - * register memory map. - * Directly initialize the struct pointer to ELM base address. - */ -struct elm { - u32 rev; /* 0x000 */ - u8 res1[12]; /* 0x004 */ - u32 sysconfig; /* 0x010 */ - u32 sysstatus; /* 0x014 */ - u32 irqstatus; /* 0x018 */ - u32 irqenable; /* 0x01c */ - u32 location_config; /* 0x020 */ - u8 res2[92]; /* 0x024 */ - u32 page_ctrl; /* 0x080 */ - u8 res3[892]; /* 0x084 */ - struct syndrome syndrome_fragments[8]; /* 0x400 */ - u8 res4[512]; /* 0x600 */ - struct location error_location[8]; /* 0x800 */ -}; - -int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, - u32 *error_locations); -int elm_config(enum bch_level level); -void elm_reset(void); -void elm_init(void); -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_ELM_H */ diff --git a/drivers/mtd/nand/omap_elm.c b/drivers/mtd/nand/omap_elm.c index 55a631deb4..47b1f1bfe2 100644 --- a/drivers/mtd/nand/omap_elm.c +++ b/drivers/mtd/nand/omap_elm.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #define ELM_DEFAULT_POLY (0) diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 452e40f04e..881a63618c 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #define BADBLOCK_MARKER_LENGTH 2 #define SECTOR_BYTES 512 diff --git a/include/linux/mtd/omap_elm.h b/include/linux/mtd/omap_elm.h new file mode 100644 index 0000000000..45454eaf0f --- /dev/null +++ b/include/linux/mtd/omap_elm.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap3 + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_ELM_H +#define __ASM_ARCH_ELM_H +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[16]; /* 0x880.... */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[8]; /* 0x400 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[8]; /* 0x800 */ +}; + +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +void elm_init(void); +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_ELM_H */ -- cgit v1.2.1