From f472069fb71c5259594bea200fb4a5ebca04c89a Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 4 Oct 2010 11:09:40 +0200 Subject: ppc4xx: Change tsr/tcr macros to upper case Remove uneccessary functions to access the TCR/TSR registers as well. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 8 ++++---- arch/powerpc/cpu/ppc4xx/interrupts.c | 7 ------- arch/powerpc/cpu/ppc4xx/traps.c | 11 +---------- 3 files changed, 5 insertions(+), 21 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index 2a727b1df3..bf208adfe6 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -342,7 +342,7 @@ cpu_init_f (void) #endif #if defined(CONFIG_WATCHDOG) - val = mfspr(tcr); + val = mfspr(SPRN_TCR); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ #elif defined(CONFIG_440EPX) @@ -354,11 +354,11 @@ cpu_init_f (void) val &= ~0x30000000; /* clear WRC bits */ val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */ #endif - mtspr(tcr, val); + mtspr(SPRN_TCR, val); - val = mfspr(tsr); + val = mfspr(SPRN_TSR); val |= 0x80000000; /* enable watchdog timer */ - mtspr(tsr, val); + mtspr(SPRN_TSR, val); reset_4xx_watchdog(); #endif /* CONFIG_WATCHDOG */ diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index c2d4973983..d0bca92f99 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -67,13 +67,6 @@ static __inline__ void set_pit(unsigned long val) asm volatile("mtpit %0" : : "r" (val)); } - -static __inline__ void set_tcr(unsigned long val) -{ - asm volatile("mttcr %0" : : "r" (val)); -} - - static __inline__ void set_evpr(unsigned long val) { asm volatile("mtevpr %0" : : "r" (val)); diff --git a/arch/powerpc/cpu/ppc4xx/traps.c b/arch/powerpc/cpu/ppc4xx/traps.c index b5562ad978..9baa7a16d1 100644 --- a/arch/powerpc/cpu/ppc4xx/traps.c +++ b/arch/powerpc/cpu/ppc4xx/traps.c @@ -46,15 +46,6 @@ extern unsigned long search_exception_table(unsigned long); */ #define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) -static __inline__ void set_tsr(unsigned long val) -{ -#if defined(CONFIG_440) - asm volatile("mtspr 0x150, %0" : : "r" (val)); -#else - asm volatile("mttsr %0" : : "r" (val)); -#endif -} - static __inline__ unsigned long get_esr(void) { unsigned long val; @@ -364,7 +355,7 @@ DecrementerPITException(struct pt_regs *regs) /* * Reset PIT interrupt */ - set_tsr(0x08000000); + mtspr(SPRN_TSR, 0x08000000); /* * Call timer_interrupt routine in interrupts.c -- cgit v1.2.1 From 834a45d7ee81ef185cc834b44b2dae7b637631e2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 7 Oct 2010 14:16:25 +0200 Subject: ppc4xx/POST: Add board specific UART POST test to lwmon5 Add CONFIG_POST_UART to implement a board specific UART POST test. This is done since lwmon5 needs to set POST_ALWAYS to run this test on each reboot. And we don't want to change the default behavious of this this. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 11 +++++++++++ post/tests.c | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index d003710125..a4e92cce3b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -193,6 +193,17 @@ #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \ CONFIG_SYS_NS16550_COM2 } +#define CONFIG_POST_UART { \ + "UART test", \ + "uart", \ + "This test verifies the UART operation.", \ + POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \ + &uart_post_test, \ + NULL, \ + NULL, \ + CONFIG_SYS_POST_UART \ + } + #define CONFIG_POST_WATCHDOG { \ "Watchdog timer test", \ "watchdog", \ diff --git a/post/tests.c b/post/tests.c index a4066f9f8b..5f59fbb27f 100644 --- a/post/tests.c +++ b/post/tests.c @@ -165,6 +165,9 @@ struct post_test post_list[] = }, #endif #if CONFIG_POST & CONFIG_SYS_POST_UART +#if defined(CONFIG_POST_UART) + CONFIG_POST_UART, +#else { "UART test", "uart", @@ -175,6 +178,7 @@ struct post_test post_list[] = NULL, CONFIG_SYS_POST_UART }, +#endif /* CONFIG_POST_UART */ #endif #if CONFIG_POST & CONFIG_SYS_POST_ETHER { -- cgit v1.2.1 From 4adcbdc6be6d01f99c6694972f150a6cce109878 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 11 Oct 2010 15:50:10 +0200 Subject: ppc4xx: Enable NOR flash support in sequoia_ramboot target Until now, the Sequoia RAM-booting image disabled NOR flash support as this image was mainly created for NAND-only boards. This patch now enables NOR flash support for this RAM-booting version as well. Signed-off-by: Stefan Roese --- board/amcc/sequoia/sequoia.c | 6 ++++-- include/configs/amcc-common.h | 11 ----------- 2 files changed, 4 insertions(+), 13 deletions(-) diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index c523bca1fe..b518aa7d72 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -155,7 +155,8 @@ int misc_init_r(void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ + defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); @@ -163,7 +164,8 @@ int misc_init_r(void) pbcr = mfdcr(EBC0_CFGDATA); size_val = ffs(gd->bd->bi_flashsize) - 21; pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); -#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) || \ + defined(CONFIG_SYS_RAMBOOT) mtdcr(EBC0_CFGADDR, PB3CR); #else mtdcr(EBC0_CFGADDR, PB0CR); diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index b9f1f6bafe..7453bf83b3 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -81,17 +81,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#if defined(CONFIG_SYS_RAMBOOT) -/* - * Disable NOR FLASH commands on RAM-booting version. One main reason for this - * RAM-booting version is boards with NAND and without NOR. This image can - * be used for initial NAND programming. - */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#endif - /* * Miscellaneous configurable options */ -- cgit v1.2.1 From acfbbb90b27971abaca1800dba22b1dc60a33369 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Oct 2010 08:41:01 +0200 Subject: ppc4xx: Fix default environment for AMCC boards Commit 0ad7f0950a9bc0a69b3cd5f34ccf7da25fcf1c6d [ppc4xx: cleanup default environment for AMCC boards] broke the default env for many PPC4xx boards. The '\0' character got removed at the end of some environment commands like "update". This patch adds the missing '\0' characters again. Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 7453bf83b3..b5d3e102b2 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -271,13 +271,13 @@ "load=tftp 200000 ${u-boot}\0" \ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}" \ + "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ "upd=run load update\0" \ #define CONFIG_AMCC_DEF_ENV_NAND_UPD \ "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ "nload=tftp 200000 ${u-boot-nand}\0" \ - "nupdate=nand erase 0 100000;nand write 200000 0 100000" \ + "nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \ "nupd=run nload nupdate\0" #endif /* __AMCC_COMMON_H */ -- cgit v1.2.1