From ca09e66b04cd2b80f95d5acc1cc7f61487034faf Mon Sep 17 00:00:00 2001 From: Wills Wang Date: Mon, 30 May 2016 22:54:54 +0800 Subject: mips: ath79: Use AR933X_PLL_SWITCH_CLOCK_CONTROL_REG macro define Add AR933X_PLL_SWITCH_CLOCK_CONTROL_REG define for ar933x chip. Signed-off-by: Wills Wang --- arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1 + arch/mips/mach-ath79/reset.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h index dabcad0d22..7b4852416b 100644 --- a/arch/mips/mach-ath79/include/mach/ar71xx_regs.h +++ b/arch/mips/mach-ath79/include/mach/ar71xx_regs.h @@ -331,6 +331,7 @@ #define AR933X_PLL_CPU_CONFIG_REG 0x00 #define AR933X_PLL_CLK_CTRL_REG 0x08 #define AR933X_PLL_DITHER_FRAC_REG 0x10 +#define AR933X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24 #define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10 #define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c index a5ee14156c..073a179baf 100644 --- a/arch/mips/mach-ath79/reset.c +++ b/arch/mips/mach-ath79/reset.c @@ -89,7 +89,7 @@ static int eth_init_ar933x(void) mdelay(10); /* Get Atheros S26 PHY out of reset. */ - clrsetbits_be32(pregs + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG, + clrsetbits_be32(pregs + AR933X_PLL_SWITCH_CLOCK_CONTROL_REG, 0x1f, 0x10); mdelay(10); -- cgit v1.2.1