From 993cad9364c6b87ae429d1ed1130d8153f6f027e Mon Sep 17 00:00:00 2001 From: wdenk Date: Thu, 26 Jun 2003 22:04:09 +0000 Subject: * Patches by Robert Schwebel, 26 Jun 2003: - logdl - csb226 - innokom * Patch by Pantelis Antoniou, 25 Jun 2003: update NetVia with V2 board support --- CHANGELOG | 8 + CREDITS | 10 +- MAKEALL | 12 +- Makefile | 14 +- board/logodl/flash.c | 678 ++++++++++++++++++++++----------------------- board/logodl/logodl.c | 16 +- board/netvia/flash.c | 22 +- board/netvia/netvia.c | 203 +++++++++----- board/netvia/u-boot.lds | 4 +- board/rsdproto/flash_asm.S | 2 +- cpu/mpc8xx/scc.c | 16 +- drivers/Makefile | 1 + drivers/serial_max3100.c | 301 ++++++++++++++++++++ include/commproc.h | 7 +- include/configs/NETVIA.h | 238 +++++++++++++--- include/configs/csb226.h | 303 ++++++++++++++++++-- include/configs/innokom.h | 4 +- include/configs/logodl.h | 17 +- include/status_led.h | 3 + include/version.h | 2 +- rtc/ds12887.c | 30 +- 21 files changed, 1365 insertions(+), 526 deletions(-) create mode 100644 drivers/serial_max3100.c diff --git a/CHANGELOG b/CHANGELOG index 0f930551f1..328703e3e9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,14 @@ Changes since U-Boot 0.3.1: ====================================================================== +* Patches by Robert Schwebel, 26 Jun 2003: + - logdl + - csb226 + - innokom + +* Patch by Pantelis Antoniou, 25 Jun 2003: + update NetVia with V2 board support + * Header file cleanup for ARM * Patch by Murray Jensen, 24 Jun 2003: diff --git a/CREDITS b/CREDITS index 756acca762..e815857c9d 100644 --- a/CREDITS +++ b/CREDITS @@ -146,6 +146,10 @@ N: Andreas Heppel E: aheppel@sysgo.de D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!] +N: August Hoeraendl +E: august.hoerandl@gmx.at +D: Support for the logodl board (PXA2xx) + N: Josh Huber E: huber@alum.wpi.edu D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. @@ -256,7 +260,7 @@ D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots mor N: Robert Schwebel E: r.schwebel@pengutronix.de -D: Support for csb226 and innokom boards (xscale) +D: Support for csb226, logodl and innokom boards (PXA2xx) N: Rob Taylor E: robt@flyingpig.com @@ -294,3 +298,7 @@ N: Alex Zuepke E: azu@sysgo.de D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM W: www.elinos.com + +N: Pantelis Antoniou +E: panto@intracom.gr +D: NETVIA board support, ARTOS support. diff --git a/MAKEALL b/MAKEALL index 6407e8488e..4dc2f9ad96 100644 --- a/MAKEALL +++ b/MAKEALL @@ -31,12 +31,12 @@ LIST_8xx=" \ IP860 IVML24 IVML24_128 IVML24_256 \ IVMS8 IVMS8_128 IVMS8_256 KUP4K \ LANTEC lwmon MBX MBX860T \ - MHPC MVS1 NETVIA NX823 \ - pcu_e R360MPI RBC823 rmu \ - RPXClassic RPXlite RRvision SM850 \ - SPD823TS svm_sc8xx SXNI855T TOP860 \ - TQM823L TQM823L_LCD TQM850L TQM855L \ - TQM860L TTTech v37 \ + MHPC MVS1 NETVIA NETVIA_V2 \ + NX823 pcu_e R360MPI RBC823 \ + rmu RPXClassic RPXlite RRvision \ + SM850 SPD823TS svm_sc8xx SXNI855T \ + TOP860 TQM823L TQM823L_LCD TQM850L \ + TQM855L TQM860L TTTech v37 \ " ######################################################################### diff --git a/Makefile b/Makefile index 3b4d78fde5..af14042926 100644 --- a/Makefile +++ b/Makefile @@ -302,8 +302,20 @@ MHPC_config: unconfig MVS1_config : unconfig @./mkconfig $(@:_config=) ppc mpc8xx mvs1 +xtract_NETVIA = $(subst _V2,,$(subst _config,,$1)) + +NETVIA_V2_config \ NETVIA_config: unconfig - @./mkconfig $(@:_config=) ppc mpc8xx netvia + @ >include/config.h + @[ -z "$(findstring NETVIA_config,$@)" ] || \ + { echo "#define CONFIG_NETVIA_VERSION 1" >>include/config.h ; \ + echo "... Version 1" ; \ + } + @[ -z "$(findstring NETVIA_V2_config,$@)" ] || \ + { echo "#define CONFIG_NETVIA_VERSION 2" >>include/config.h ; \ + echo "... Version 2" ; \ + } + @./mkconfig -a $(call xtract_NETVIA,$@) ppc mpc8xx netvia NX823_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx nx823 diff --git a/board/logodl/flash.c b/board/logodl/flash.c index 0240c72362..3837401fd3 100644 --- a/board/logodl/flash.c +++ b/board/logodl/flash.c @@ -26,9 +26,9 @@ #include #define FLASH_BANK_SIZE 0x1000000 -#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ +#define MAIN_SECT_SIZE 0x20000 /* 2x64k = 128k per sector */ -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it * has nothing to do with the flash chip being 8-bit or 16-bit. @@ -53,16 +53,14 @@ typedef volatile unsigned long FLASH_PORT_WIDTHV; /*----------------------------------------------------------------------- * Functions */ -static ulong flash_get_size (FPWV * addr, flash_info_t * info); -static void flash_reset (flash_info_t * info); -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); - +static ulong flash_get_size(FPWV *addr, flash_info_t *info); +static void flash_reset(flash_info_t *info); +static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); +static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); #define write_word(in, de, da) write_word_amd(in, de, da) -static void flash_get_offsets (ulong base, flash_info_t * info); - +static void flash_get_offsets(ulong base, flash_info_t *info); #ifdef CFG_FLASH_PROTECTION -static void flash_sync_real_protect (flash_info_t * info); +static void flash_sync_real_protect(flash_info_t *info); #endif /*----------------------------------------------------------------------- @@ -70,95 +68,99 @@ static void flash_sync_real_protect (flash_info_t * info); * * sets up flash_info and returns size of FLASH (bytes) */ -ulong flash_init (void) +ulong flash_init(void) { - int i, j; - ulong size = 0; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CFG_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = PHYS_FLASH_1; - break; - case 1: - flashbase = PHYS_FLASH_2; - break; - default: - panic ("configured to many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; + int i, j; + ulong size = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) + { + ulong flashbase = 0; + flash_info[i].flash_id = + (FLASH_MAN_AMD & FLASH_VENDMASK) | + (FLASH_AM640U & FLASH_TYPEMASK); + flash_info[i].size = FLASH_BANK_SIZE; + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); + switch (i) + { + case 0: + flashbase = PHYS_FLASH_1; + break; + case 1: + flashbase = PHYS_FLASH_2; + break; + default: + panic("configured to many flash banks!\n"); + break; + } + for (j = 0; j < flash_info[i].sector_count; j++) + { + flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CFG_FLASH_BASE, - CFG_FLASH_BASE + _armboot_end_data - _armboot_start, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); - - return size; + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + _armboot_end_data - _armboot_start, + &flash_info[0]); + + flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + + return size; } /*----------------------------------------------------------------------- */ -static void flash_reset (flash_info_t * info) +static void flash_reset(flash_info_t *info) { - FPWV *base = (FPWV *) (info->start[0]); + FPWV *base = (FPWV *)(info->start[0]); /* Put FLASH back in read mode */ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ + *base = (FPW)0x00FF00FF; /* Intel Read Mode */ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ + *base = (FPW)0x00F000F0; /* AMD Read Mode */ } /*----------------------------------------------------------------------- */ -static void flash_get_offsets (ulong base, flash_info_t * info) +static void flash_get_offsets (ulong base, flash_info_t *info) { int i; /* set up sector start address table */ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ + && (info->flash_id & FLASH_BTYPE)) { + int bootsect_size; /* number of bytes/boot sector */ int sect_size; /* number of bytes/regular sector */ - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); + bootsect_size = 0x00002000 * (sizeof(FPW)/2); + sect_size = 0x00010000 * (sizeof(FPW)/2); - /* set sector offsets for bottom boot block type */ + /* set sector offsets for bottom boot block type */ for (i = 0; i < 8; ++i) { info->start[i] = base + (i * bootsect_size); } for (i = 8; i < info->sector_count; i++) { info->start[i] = base + ((i - 7) * sect_size); } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { + } + else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD + && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { int sect_size; /* number of bytes/sector */ - sect_size = 0x00010000 * (sizeof (FPW) / 2); + sect_size = 0x00010000 * (sizeof(FPW)/2); /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) + for( i = 0; i < info->sector_count; i++ ) info->start[i] = base + (i * sect_size); } } @@ -166,7 +168,7 @@ static void flash_get_offsets (ulong base, flash_info_t * info) /*----------------------------------------------------------------------- */ -void flash_print_info (flash_info_t * info) +void flash_print_info (flash_info_t *info) { int i; uchar *boottype; @@ -183,34 +185,21 @@ void flash_print_info (flash_info_t * info) } switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf ("AMD "); - break; - case FLASH_MAN_BM: - printf ("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf ("FUJITSU "); - break; - case FLASH_MAN_SST: - printf ("SST "); - break; - case FLASH_MAN_STM: - printf ("STM "); - break; - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; + case FLASH_MAN_AMD: printf ("AMD "); break; + case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; + case FLASH_MAN_FUJ: printf ("FUJITSU "); break; + case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("STM "); break; + case FLASH_MAN_INTEL: printf ("INTEL "); break; + default: printf ("Unknown Vendor "); break; } /* check for top or bottom boot, if it applies */ if (info->flash_id & FLASH_BTYPE) { boottype = botboottype; bootletter = botbootletter; - } else { + } + else { boottype = topboottype; bootletter = topbootletter; } @@ -219,32 +208,32 @@ void flash_print_info (flash_info_t * info) case FLASH_AM640U: fmt = "29LV641D (64 Mbit, uniform sectors)\n"; break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: + case FLASH_28F800C3B: + case FLASH_28F800C3T: fmt = "28F800C3%s (8 Mbit, %s)\n"; break; case FLASH_INTEL800B: case FLASH_INTEL800T: fmt = "28F800B3%s (8 Mbit, %s)\n"; break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: fmt = "28F160C3%s (16 Mbit, %s)\n"; break; case FLASH_INTEL160B: case FLASH_INTEL160T: fmt = "28F160B3%s (16 Mbit, %s)\n"; break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: fmt = "28F320C3%s (32 Mbit, %s)\n"; break; case FLASH_INTEL320B: case FLASH_INTEL320T: fmt = "28F320B3%s (32 Mbit, %s)\n"; break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: fmt = "28F640C3%s (64 Mbit, %s)\n"; break; case FLASH_INTEL640B: @@ -259,11 +248,12 @@ void flash_print_info (flash_info_t * info) printf (fmt, bootletter, boottype); printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); + info->size >> 20, + info->sector_count); printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { + for (i=0; isector_count; ++i) { if ((i % 5) == 0) { printf ("\n "); } @@ -282,25 +272,25 @@ void flash_print_info (flash_info_t * info) * The following code cannot be run from FLASH! */ -ulong flash_get_size (FPWV * addr, flash_info_t * info) +ulong flash_get_size (FPWV *addr, flash_info_t *info) { /* Write auto select command: read Manufacturer ID */ /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ + addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ + addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */ + addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */ /* The manufacturer codes are only 1 byte, so just use 1 byte. * This works for any bus width and any FLASH device width. */ switch (addr[0] & 0xff) { - case (uchar) AMD_MANUFACT: + case (uchar)AMD_MANUFACT: info->flash_id = FLASH_MAN_AMD; break; - case (uchar) INTEL_MANUFACT: + case (uchar)INTEL_MANUFACT: info->flash_id = FLASH_MAN_INTEL; break; @@ -312,74 +302,73 @@ ulong flash_get_size (FPWV * addr, flash_info_t * info) } /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } + if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) { + + case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ + info->flash_id += FLASH_AM640U; + info->sector_count = 128; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F800C3B: + info->flash_id += FLASH_28F800C3B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F800B3B: + info->flash_id += FLASH_INTEL800B; + info->sector_count = 23; + info->size = 0x00100000 * (sizeof(FPW)/2); + break; /* => 1 or 2 MB */ + + case (FPW)INTEL_ID_28F160C3B: + info->flash_id += FLASH_28F160C3B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F160B3B: + info->flash_id += FLASH_INTEL160B; + info->sector_count = 39; + info->size = 0x00200000 * (sizeof(FPW)/2); + break; /* => 2 or 4 MB */ + + case (FPW)INTEL_ID_28F320C3B: + info->flash_id += FLASH_28F320C3B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F320B3B: + info->flash_id += FLASH_INTEL320B; + info->sector_count = 71; + info->size = 0x00400000 * (sizeof(FPW)/2); + break; /* => 4 or 8 MB */ + + case (FPW)INTEL_ID_28F640C3B: + info->flash_id += FLASH_28F640C3B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ + + case (FPW)INTEL_ID_28F640B3B: + info->flash_id += FLASH_INTEL640B; + info->sector_count = 135; + info->size = 0x00800000 * (sizeof(FPW)/2); + break; /* => 8 or 16 MB */ - flash_get_offsets ((ulong) addr, info); + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* => no or unknown flash */ + } + + flash_get_offsets((ulong)addr, info); /* Put FLASH back in read mode */ - flash_reset (info); + flash_reset(info); return (info->size); } @@ -388,50 +377,50 @@ ulong flash_get_size (FPWV * addr, flash_info_t * info) /*----------------------------------------------------------------------- */ -static void flash_sync_real_protect (flash_info_t * info) +static void flash_sync_real_protect(flash_info_t *info) { - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset (info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; + FPWV *addr = (FPWV *)(info->start[0]); + FPWV *sect; + int i; + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F800C3B: + case FLASH_28F800C3T: + case FLASH_28F160C3B: + case FLASH_28F160C3T: + case FLASH_28F320C3B: + case FLASH_28F320C3T: + case FLASH_28F640C3B: + case FLASH_28F640C3T: + /* check for protected sectors */ + *addr = (FPW)0x00900090; + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02. + * D0 = 1 for each device if protected. + * If at least one device is protected the sector is marked + * protected, but mixed protected and unprotected devices + * within a sector should never happen. + */ + sect = (FPWV *)(info->start[i]); + info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0; } + + /* Put FLASH back in read mode */ + flash_reset(info); + break; + + case FLASH_AM640U: + default: + /* no hardware protect that we support */ + break; + } } #endif /*----------------------------------------------------------------------- */ -int flash_erase (flash_info_t * info, int s_first, int s_last) +int flash_erase (flash_info_t *info, int s_first, int s_last) { FPWV *addr; int flag, prot, sect; @@ -467,7 +456,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { + for (sect=s_first; sect<=s_last; ++sect) { if (info->protect[sect]) { prot++; } @@ -475,60 +464,61 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) if (prot) { printf ("- Warning: %d protected sectors will not be erased!\n", - prot); + prot); } else { printf ("\n"); } - start = get_timer (0); - last = start; + start = get_timer(0); + last = start; /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { + for (sect = s_first; sect<=s_last && rcode == 0; sect++) { if (info->protect[sect] != 0) /* protected, skip it */ continue; /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + flag = disable_interrupts(); - addr = (FPWV *) (info->start[sect]); + addr = (FPWV *)(info->start[sect]); if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { + *addr = (FPW)0x00500050; /* clear status register */ + *addr = (FPW)0x00200020; /* erase setup */ + *addr = (FPW)0x00D000D0; /* erase confirm */ + } + else { /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ + FPWV *base; /* first address in bank */ + + base = (FPWV *)(info->start[0]); + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00800080; /* erase mode */ + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + *addr = (FPW)0x00300030; /* erase sector */ } /* re-enable interrupts if necessary */ if (flag) - enable_interrupts (); + enable_interrupts(); /* wait at least 50us for AMD, 80us for Intel. * Let's wait 1 ms. */ udelay (1000); - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { + while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { printf ("Timeout\n"); if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; + /* suspend erase */ + *addr = (FPW)0x00B000B0; } - flash_reset (info); /* reset to read mode */ + flash_reset(info); /* reset to read mode */ rcode = 1; /* failed */ break; } @@ -540,7 +530,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) } } - flash_reset (info); /* reset to read mode */ + flash_reset(info); /* reset to read mode */ } printf (" done\n"); @@ -555,48 +545,46 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) */ int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { - FPW data = 0; /* 16 or 32 bit word, matches flash bus width */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - /* printf("write_buff: src: %8p addr %08lx count: %ld\n", src, addr, cnt); */ + FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof(data), left -= sizeof(data) - bytes) { - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); + bytes = addr & (sizeof(data) - 1); + addr &= ~(sizeof(data) - 1); - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof(data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left ) + data += *((uchar *)addr + i); + else + data += *src++; + } - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd (info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel (info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } + /* write one word to the flash */ + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + res = write_word_amd(info, (FPWV *)addr, data); + break; + case FLASH_MAN_INTEL: + res = write_word_intel(info, (FPWV *)addr, data); + break; + default: + /* unknown flash type, error! */ + printf ("missing or unknown FLASH type\n"); + res = 1; /* not really a timeout, but gives error */ + break; } + } - return (res); + return (res); } /** @@ -610,7 +598,7 @@ int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) * @return error code */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { ulong cp, wp; FPW data; @@ -624,19 +612,19 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) */ if ((l = addr - wp) != 0) { data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); + for (i=0, cp=wp; i> 8) | (*(uchar *)cp << 8); } - for (; i < 2 && cnt > 0; ++i) { + for (; i<2 && cnt>0; ++i) { data = (data >> 8) | (*src++ << 8); --cnt; ++cp; } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); + for (; cnt==0 && i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); } - if ((rc = write_word (info, wp, data)) != 0) { + if ((rc = write_word(info, wp, data)) != 0) { return (rc); } wp += 2; @@ -647,31 +635,30 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) */ while (cnt >= 2) { /* data = *((vushort*)src); */ - data = *((FPW *) src); - if ((rc = write_word (info, wp, data)) != 0) { + data = *((FPW*)src); + if ((rc = write_word(info, wp, data)) != 0) { return (rc); } - src += sizeof (FPW); - wp += sizeof (FPW); - cnt -= sizeof (FPW); + src += sizeof(FPW); + wp += sizeof(FPW); + cnt -= sizeof(FPW); } - if (cnt == 0) - return ERR_OK; + if (cnt == 0) return ERR_OK; /* * handle unaligned tail bytes */ data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { data = (data >> 8) | (*src++ << 8); --cnt; } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); + for (; i<2; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 8); } - return write_word (info, wp, data); + return write_word(info, wp, data); } @@ -686,45 +673,44 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) * 1 - write timeout * 2 - Flash not erased */ -static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) +static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) { - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } - base = (FPWV *) (info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ + base = (FPWV *)(info->start[0]); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - *dest = data; /* start programming the data */ + base[0x0555] = (FPW)0x00AA00AA; /* unlock */ + base[0x02AA] = (FPW)0x00550055; /* unlock */ + base[0x0555] = (FPW)0x00A000A0; /* selects program mode */ - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); + *dest = data; /* start programming the data */ - start = get_timer (0); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - res = 1; - } + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00F000F0; /* reset bank */ + res = 1; } + } - return (res); + return (res); } /*----------------------------------------------------------------------- @@ -737,46 +723,46 @@ static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) * 1 - write timeout * 2 - Flash not erased */ -static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) +static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) { - ulong start; - int flag; - int res = 0; /* result, assume success */ + ulong start; + int flag; + int res = 0; /* result, assume success */ - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00400040; /* program setup */ - *dest = data; /* start programming the data */ + *dest = data; /* start programming the data */ - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts (); + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); - start = get_timer (0); + start = get_timer (0); - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } + while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW)0x00B000B0; /* Suspend program */ + res = 1; } + } - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ + if (res == 0 && (*dest & (FPW)0x00100010)) + res = 1; /* write failed, time out error is close enough */ - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ + *dest = (FPW)0x00500050; /* clear status register */ + *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - return (res); + return (res); } #ifdef CFG_FLASH_PROTECTION @@ -784,8 +770,8 @@ static int write_word_intel (flash_info_t * info, FPWV * dest, FPW data) */ int flash_real_protect (flash_info_t * info, long sector, int prot) { - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ + int rcode = 0; /* assume success */ + FPWV *addr; /* address of sector */ FPW value; addr = (FPWV *) (info->start[sector]); @@ -826,7 +812,7 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) info->protect[sector] = 1; } if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ + rcode = 1; /* failed to protect/unprotect as requested */ /* reload all protection bits from hardware for now */ flash_sync_real_protect (info); diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index a46452c4e6..f16c05bb65 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -1,7 +1,7 @@ /* * (C) 2002 Kyle Harris , Nexus Technologies, Inc. * (C) 2002 Marius Groeger , Sysgo GmbH - * (C) 2003 Robert Schwebel , Pengutronix + * (C) 2003 Robert Schwebel , Pengutronix * * See file CREDITS for list of people who contributed to this * project. @@ -66,7 +66,7 @@ int dram_init (void) } -/** +/** * logodl_set_led: - switch LEDs on or off * * @param led: LED to switch (0,1) @@ -77,15 +77,15 @@ void logodl_set_led(int led, int state) { switch(led) { - case 0: - if (state==1) { + case 0: + if (state==1) { CFG_LED_A_CR = CFG_LED_A_BIT; } else if (state==0) { CFG_LED_A_SR = CFG_LED_A_BIT; } break; - case 1: + case 1: if (state==1) { CFG_LED_B_CR = CFG_LED_B_BIT; } else if (state==0) { @@ -93,7 +93,7 @@ void logodl_set_led(int led, int state) } break; } - + return; } @@ -101,9 +101,9 @@ void logodl_set_led(int led, int state) /** * show_boot_progress: - indicate state of the boot process * - * @param status: Status number - see README for details. + * @param status: Status number - see README for details. * - * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most + * The LOGOTRONIC does only have 2 LEDs, so we switch them on at the most * important states (1, 5, 15). */ diff --git a/board/netvia/flash.c b/board/netvia/flash.c index 669031f735..d31f7707f7 100644 --- a/board/netvia/flash.c +++ b/board/netvia/flash.c @@ -44,11 +44,8 @@ unsigned long flash_init(void) int i; /* Init: no FLASHes known */ - for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]); @@ -66,7 +63,22 @@ unsigned long flash_init(void) flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]); /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); + flash_protect(FLAG_PROTECT_SET, + CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1, + &flash_info[0]); + + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, + &flash_info[0]); + +#ifdef CFG_ENV_ADDR_REDUND + flash_protect ( FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[0]); +#endif + flash_info[0].size = size; diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c index 504593effe..9dd732b3c2 100644 --- a/board/netvia/netvia.c +++ b/board/netvia/netvia.c @@ -29,6 +29,17 @@ #include #include "mpc8xx.h" +/****************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +/* last value written to the external register; we cannot read back */ +unsigned int last_er_val; +#endif + +/****************************************************************/ + +/****************************************************************/ + /* some sane bit macros */ #define _BD(_b) (1U << (31-(_b))) #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1)) @@ -42,13 +53,11 @@ #define _B(_b) _BD(_b) #define _BR(_l, _h) _BDR(_l, _h) -/* ------------------------------------------------------------------------- */ - -/* ------------------------------------------------------------------------- */ +/****************************************************************/ #define _NOT_USED_ 0xFFFFFFFF -/* ------------------------------------------------------------------------- */ +/****************************************************************/ #define CS_0000 0x00000000 #define CS_0001 0x10000000 @@ -208,7 +217,11 @@ const uint sdram_table[0x40] = { int checkboard(void) { - printf ("NETVIA\n"); +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + printf ("NETVIA v1\n"); +#else + printf ("NETVIA v2+\n"); +#endif return (0); } @@ -275,25 +288,6 @@ long int initdram(int board_type) udelay(10000); - /* do the ram test */ - { - register unsigned long *rp; - register unsigned long v; - - /* first fill */ - for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; ) - *rp++ = (unsigned long)rp; - - /* now check */ - for (rp = (unsigned long *)0; rp < (unsigned long *)SDRAM_MAX_SIZE; rp++) { - if ((v = *rp) != (unsigned long)rp) { - printf("ERROR at 0x%lx (0x%lx)\n", (unsigned long)rp, v); - return -1; - } - } - - } - return (size); } @@ -301,74 +295,141 @@ long int initdram(int board_type) int misc_init_r(void) { +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + last_er_val = 0xffffffff; +#endif return(0); } /* ------------------------------------------------------------------------- */ +/* GP = general purpose, SP = special purpose (on chip peripheral) */ + /* bits that can have a special purpose or can be configured as inputs/outputs */ -#define PA_MASK (_BWR(4, 9) | _BWR(12, 15)) -#define PA_ODR_MASK (_BW(9) | _BW(12) | _BW(14)) -#define PA_ODR_VAL 0 #define PA_GP_INMASK 0 -#define PA_GP_OUTMASK (_BW(5) | _BW(14) | _BW(15)) -#define PA_SP_OUTMASK 0 +#define PA_GP_OUTMASK (_BW(5) | _BWR(14, 15)) +#define PA_SP_MASK (_BW(4) | _BWR(6, 13)) +#define PA_ODR_VAL 0 #define PA_GP_OUTVAL _BW(5) -#define PA_SP_OUTVAL 0 +#define PA_SP_DIRVAL 0 -#define PB_MASK (_BR(16, 19) | _BR(22, 31)) -#define PB_ODR_MASK PB_MASK +#define PB_GP_INMASK _B(28) +#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_MASK _BR(22, 25) #define PB_ODR_VAL 0 -#define PB_GP_INMASK 0 -#define PB_GP_OUTMASK (_BR(16, 19) | _BR(26, 27) | _B(31)) -#define PB_SP_OUTMASK _BR(28, 30) -#define PB_SP_OUTVAL _BR(28, 30) -#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _B(31)) - -#define PC_MASK _BWR(4, 15) -#define PC_SO_MASK (_BWR(6, 11) | _BWR(14, 15)) -#define PC_SO_VAL 0 -#define PC_INT_MASK PC_MASK -#define PC_INT_VAL 0 +#define PB_GP_OUTVAL (_BR(16, 19) | _BR(26, 27) | _BR(29, 31)) +#define PB_SP_DIRVAL 0 + +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + #define PC_GP_INMASK (_BWR(5, 7) | _BWR(9, 10) | _BW(13)) #define PC_GP_OUTMASK _BW(12) -#define PC_SP_OUTMASK 0 -#define PC_SP_OUTVAL _BW(12) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL 0 #define PC_GP_OUTVAL 0 +#define PC_SP_DIRVAL 0 -#define PD_MASK _BWR(0, 15) #define PD_GP_INMASK 0 #define PD_GP_OUTMASK _BWR(3, 15) -#define PD_SP_OUTMASK 0 +#define PD_SP_MASK 0 #define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(7) | _BWR(8, 15)) -#define PD_SP_OUTVAL 0 +#define PD_SP_DIRVAL 0 + +#elif CONFIG_NETVIA_VERSION >= 2 + +#define PC_GP_INMASK (_BW(5) | _BW(7) | _BWR(9, 11) | _BWR(13, 15)) +#define PC_GP_OUTMASK (_BW(6) | _BW(12)) +#define PC_SP_MASK (_BW(4) | _BW(8)) +#define PC_SOVAL 0 +#define PC_INTVAL _BW(7) +#define PC_GP_OUTVAL (_BW(6) | _BW(12)) +#define PC_SP_DIRVAL 0 + +#define PD_GP_INMASK 0 +#define PD_GP_OUTMASK _BWR(3, 15) +#define PD_SP_MASK 0 +#define PD_GP_OUTVAL (_BW(3) | _BW(5) | _BW(9) | _BW(11)) +#define PD_SP_DIRVAL 0 + +#else +#error Unknown NETVIA board version. +#endif int board_pre_init(void) { - register volatile immap_t *immap = (immap_t *) CFG_IMMR; - register volatile iop8xx_t *ioport = &immap->im_ioport; - register volatile cpm8xx_t *cpm = &immap->im_cpm; - - ioport->iop_padat = (ioport->iop_padat & ~PA_MASK) | PA_SP_OUTVAL | PA_GP_OUTVAL; - ioport->iop_paodr = (ioport->iop_paodr & ~PA_ODR_MASK) | PA_ODR_VAL; - ioport->iop_padir = (ioport->iop_padir & ~PA_GP_INMASK)| PA_SP_OUTMASK | PA_GP_OUTMASK; - ioport->iop_papar = (ioport->iop_papar & ~(PA_GP_INMASK & PA_GP_OUTMASK)); - - cpm->cp_pbdat = (ioport->iop_padat & ~PB_MASK) | PB_SP_OUTVAL | PB_GP_OUTVAL; - cpm->cp_pbodr = (ioport->iop_paodr & ~PB_ODR_MASK) | PB_ODR_VAL; - cpm->cp_pbdir = (ioport->iop_padir & ~PB_GP_INMASK)| PB_SP_OUTMASK | PB_GP_OUTMASK; - cpm->cp_pbpar = (ioport->iop_papar & ~(PB_GP_INMASK & PB_GP_OUTMASK)); - - ioport->iop_pcdat = (ioport->iop_pcdat & ~PC_MASK) | PC_SP_OUTVAL | PC_GP_OUTVAL; - ioport->iop_pcdir = (ioport->iop_pcdir & ~PC_GP_INMASK)| PC_SP_OUTMASK | PC_GP_OUTMASK; - ioport->iop_pcso = (ioport->iop_pcso & ~PC_SO_MASK) | PC_SO_VAL; - ioport->iop_pcint = (ioport->iop_pcint & ~PC_INT_MASK) | PC_INT_VAL; - ioport->iop_pcpar = (ioport->iop_pcpar & ~(PC_GP_INMASK & PC_GP_OUTMASK)); - - ioport->iop_pddat = (ioport->iop_pddat & ~PD_MASK) | PD_SP_OUTVAL | PD_GP_OUTVAL; - ioport->iop_pddir = (ioport->iop_pddir & ~PD_GP_INMASK)| PD_SP_OUTMASK | PD_GP_OUTMASK; - ioport->iop_pdpar = (ioport->iop_pdpar & ~(PD_GP_INMASK & PD_GP_OUTMASK)); + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile iop8xx_t *ioport = &immap->im_ioport; + volatile cpm8xx_t *cpm = &immap->im_cpm; + volatile memctl8xx_t *memctl = &immap->im_memctl; + + /* DSP0 chip select */ + memctl->memc_or4 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br4 = ((DSP0_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* DSP1 chip select */ + memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX); + memctl->memc_br5 = ((DSP1_BASE & BR_BA_MSK) | BR_PS_16 | BR_V); + + /* FPGA chip select */ + memctl->memc_or6 = ((0xFFFFFFFFLU & ~(FPGA_SIZE - 1)) | OR_BI | OR_SCY_1_CLK); + memctl->memc_br6 = ((FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + /* NAND chip select */ + memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX); + memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + + /* kill this chip select */ + memctl->memc_br2 &= ~BR_V; /* invalid */ + + /* external reg chip select */ + memctl->memc_or7 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK); + memctl->memc_br7 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V); +#endif + + ioport->iop_padat = PA_GP_OUTVAL; + ioport->iop_paodr = PA_ODR_VAL; + ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL; + ioport->iop_papar = PA_SP_MASK; + + cpm->cp_pbdat = PB_GP_OUTVAL; + cpm->cp_pbodr = PB_ODR_VAL; + cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL; + cpm->cp_pbpar = PB_SP_MASK; + + ioport->iop_pcdat = PC_GP_OUTVAL; + ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL; + ioport->iop_pcso = PC_SOVAL; + ioport->iop_pcint = PC_INTVAL; + ioport->iop_pcpar = PC_SP_MASK; + + ioport->iop_pddat = PD_GP_OUTVAL; + ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL; + ioport->iop_pdpar = PD_SP_MASK; + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + /* external register init */ + *(volatile uint *)ER_BASE = 0xFFFFFFFF; +#endif return 0; } +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include + +extern void nand_probe(ulong physadr); +extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; + +void nand_init(void) +{ + nand_probe(CFG_NAND_BASE); + if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { + nand_dev_desc[0].name = "NetVia NAND flash"; + puts("NAND: "); + print_size(nand_dev_desc[0].totlen, "\n"); + } +} +#endif diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index 35e00f4dfd..5ac88da4f6 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -63,8 +63,8 @@ SECTIONS lib_ppc/cache.o (.text) lib_ppc/time.o (.text) - . = env_offset; - common/environment.o (.ppcenv) + . = DEFINED(env_offset) ? env_offset : .; + common/environment.o (.text) *(.text) *(.fixup) diff --git a/board/rsdproto/flash_asm.S b/board/rsdproto/flash_asm.S index c65fb87040..557cac0279 100644 --- a/board/rsdproto/flash_asm.S +++ b/board/rsdproto/flash_asm.S @@ -26,7 +26,7 @@ #include #include -.globl ull_write + .globl ull_write ull_write: lfd 0,0(r4) stfd 0,0(r3) diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 4ff23c3b68..f98aad4011 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -494,14 +494,22 @@ static int scc_init(struct eth_device* dev, bd_t *bis) #endif #if defined(CONFIG_NETVIA) -#if defined(PB_ENET_PDN) +#if defined(PA_ENET_PDN) + immr->im_ioport.iop_papar &= ~PA_ENET_PDN; + immr->im_ioport.iop_padir |= PA_ENET_PDN; + immr->im_ioport.iop_padat |= PA_ENET_PDN; +#elif defined(PB_ENET_PDN) immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN; immr->im_cpm.cp_pbdir |= PB_ENET_PDN; immr->im_cpm.cp_pbdat |= PB_ENET_PDN; #elif defined(PC_ENET_PDN) - immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN; - immr->im_cpm.cp_pcdir |= PC_ENET_PDN; - immr->im_cpm.cp_pcdat |= PC_ENET_PDN; + immr->im_ioport.iop_pcpar &= ~PC_ENET_PDN; + immr->im_ioport.iop_pcdir |= PC_ENET_PDN; + immr->im_ioport.iop_pcdat |= PC_ENET_PDN; +#elif defined(PD_ENET_PDN) + immr->im_ioport.iop_pdpar &= ~PD_ENET_PDN; + immr->im_ioport.iop_pddir |= PD_ENET_PDN; + immr->im_ioport.iop_pddat |= PD_ENET_PDN; #endif #endif diff --git a/drivers/Makefile b/drivers/Makefile index 8eb9472d0d..f1ea1178e2 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -37,6 +37,7 @@ OBJS = 3c589.o 5701rls.o ali512x.o \ pci.o pci_auto.o pci_indirect.o \ pcnet.o plb2800_eth.o \ s3c24x0_i2c.o sed13806.o serial.o \ + serial_max3100.o \ smc91111.o smiLynxEM.o sym53c8xx.o \ ti_pci1410a.o tigon3.o w83c553f.o \ status_led.o diff --git a/drivers/serial_max3100.c b/drivers/serial_max3100.c new file mode 100644 index 0000000000..bbe212b81f --- /dev/null +++ b/drivers/serial_max3100.c @@ -0,0 +1,301 @@ +/* + * (C) Copyright 2003 + * + * Pantelis Antoniou + * Intracom S.A. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#ifdef CONFIG_MAX3100_SERIAL + +/**************************************************************/ + +/* convienient macros */ +#define MAX3100_SPI_RXD() (MAX3100_SPI_RXD_PORT & MAX3100_SPI_RXD_BIT) + +#define MAX3100_SPI_TXD(x) \ + do { \ + if (x) \ + MAX3100_SPI_TXD_PORT |= MAX3100_SPI_TXD_BIT; \ + else \ + MAX3100_SPI_TXD_PORT &= ~MAX3100_SPI_TXD_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK(x) \ + do { \ + if (x) \ + MAX3100_SPI_CLK_PORT |= MAX3100_SPI_CLK_BIT; \ + else \ + MAX3100_SPI_CLK_PORT &= ~MAX3100_SPI_CLK_BIT; \ + } while(0) + +#define MAX3100_SPI_CLK_TOGGLE() (MAX3100_SPI_CLK_PORT ^= MAX3100_SPI_CLK_BIT) + +#define MAX3100_CS(x) \ + do { \ + if (x) \ + MAX3100_CS_PORT |= MAX3100_CS_BIT; \ + else \ + MAX3100_CS_PORT &= ~MAX3100_CS_BIT; \ + } while(0) + +/**************************************************************/ + +/* MAX3100 definitions */ + +#define MAX3100_WC (3 << 14) /* write configuration */ +#define MAX3100_RC (1 << 14) /* read configuration */ +#define MAX3100_WD (2 << 14) /* write data */ +#define MAX3100_RD (0 << 14) /* read data */ + +/* configuration register bits */ +#define MAX3100_FEN (1 << 13) /* FIFO enable */ +#define MAX3100_SHDN (1 << 12) /* shutdown bit */ +#define MAX3100_TM (1 << 11) /* T bit irq mask */ +#define MAX3100_RM (1 << 10) /* R bit irq mask */ +#define MAX3100_PM (1 << 9) /* P bit irq mask */ +#define MAX3100_RAM (1 << 8) /* mask for RA/FE bit */ +#define MAX3100_IR (1 << 7) /* IRDA timing mode */ +#define MAX3100_ST (1 << 6) /* transmit stop bit */ +#define MAX3100_PE (1 << 5) /* parity enable bit */ +#define MAX3100_L (1 << 4) /* Length bit */ +#define MAX3100_B_MASK (0x000F) /* baud rate bits mask */ +#define MAX3100_B(x) ((x) & 0x000F) /* baud rate select bits */ + +/* data register bits (write) */ +#define MAX3100_TE (1 << 10) /* transmit enable bit (active low) */ +#define MAX3100_RTS (1 << 9) /* request-to-send bit (inverted ~RTS pin) */ + +/* data register bits (read) */ +#define MAX3100_RA (1 << 10) /* receiver activity when in shutdown mode */ +#define MAX3100_FE (1 << 10) /* framing error when in normal mode */ +#define MAX3100_CTS (1 << 9) /* clear-to-send bit (inverted ~CTS pin) */ + +/* data register bits (both directions) */ +#define MAX3100_R (1 << 15) /* receive bit */ +#define MAX3100_T (1 << 14) /* transmit bit */ +#define MAX3100_P (1 << 8) /* parity bit */ +#define MAX3100_D_MASK 0x00FF /* data bits mask */ +#define MAX3100_D(x) ((x) & 0x00FF) /* data bits */ + +/* these definitions are valid only for fOSC = 3.6864MHz */ +#define MAX3100_B_230400 MAX3100_B(0) +#define MAX3100_B_115200 MAX3100_B(1) +#define MAX3100_B_57600 MAX3100_B(2) +#define MAX3100_B_38400 MAX3100_B(9) +#define MAX3100_B_19200 MAX3100_B(10) +#define MAX3100_B_9600 MAX3100_B(11) +#define MAX3100_B_4800 MAX3100_B(12) +#define MAX3100_B_2400 MAX3100_B(13) +#define MAX3100_B_1200 MAX3100_B(14) +#define MAX3100_B_600 MAX3100_B(15) + +/**************************************************************/ + +static inline unsigned int max3100_transfer(unsigned int val) +{ + unsigned int rx; + int b; + + MAX3100_SPI_CLK(0); + MAX3100_CS(0); + + rx = 0; b = 16; + while (--b >= 0) { + MAX3100_SPI_TXD(val & 0x8000); + val <<= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + rx <<= 1; + if (MAX3100_SPI_RXD()) + rx |= 1; + MAX3100_SPI_CLK_TOGGLE(); + udelay(1); + } + + MAX3100_SPI_CLK(1); + MAX3100_CS(1); + + return rx; +} + +/**************************************************************/ + +/* must be power of 2 */ +#define RXFIFO_SZ 16 + +static int rxfifo_cnt; +static int rxfifo_in; +static int rxfifo_out; +static unsigned char rxfifo_buf[16]; + +static void max3100_putc(int c) +{ + unsigned int rx; + + while (((rx = max3100_transfer(MAX3100_RC)) & MAX3100_T) == 0) + WATCHDOG_RESET(); + + rx = max3100_transfer(MAX3100_WD | (c & 0xff)); + if ((rx & MAX3100_RD) != 0 && rxfifo_cnt < RXFIFO_SZ) { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + } +} + +static int max3100_getc(void) +{ + int c; + unsigned int rx; + + while (rxfifo_cnt == 0) { + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) != 0) { + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + } + WATCHDOG_RESET(); + } + + rxfifo_cnt--; + c = rxfifo_buf[rxfifo_out++]; + rxfifo_out &= RXFIFO_SZ - 1; + return c; +} + +static int max3100_tstc(void) +{ + unsigned int rx; + + if (rxfifo_cnt > 0) + return 1; + + rx = max3100_transfer(MAX3100_RD); + if ((rx & MAX3100_R) == 0) + return 0; + + do { + rxfifo_cnt++; + rxfifo_buf[rxfifo_in++] = rx & 0xff; + rxfifo_in &= RXFIFO_SZ - 1; + + if (rxfifo_cnt >= RXFIFO_SZ) + break; + } while (((rx = max3100_transfer(MAX3100_RD)) & MAX3100_R) != 0); + + return 1; +} + +int serial_init(void) +{ + unsigned int wconf, rconf; + int i; + DECLARE_GLOBAL_DATA_PTR; + + wconf = 0; + + /* Set baud rate */ + switch (gd->baudrate) { + case 1200: + wconf = MAX3100_B_1200; + break; + case 2400: + wconf = MAX3100_B_2400; + break; + case 4800: + wconf = MAX3100_B_4800; + break; + case 9600: + wconf = MAX3100_B_9600; + break; + case 19200: + wconf = MAX3100_B_19200; + break; + case 38400: + wconf = MAX3100_B_38400; + break; + case 57600: + wconf = MAX3100_B_57600; + break; + default: + case 115200: + wconf = MAX3100_B_115200; + break; + case 230400: + wconf = MAX3100_B_230400; + break; + } + + /* try for 10ms, with a 100us gap */ + for (i = 0; i < 10000; i += 100) { + + max3100_transfer(MAX3100_WC | wconf); + rconf = max3100_transfer(MAX3100_RC) & 0x3fff; + + if (rconf == wconf) + break; + udelay(100); + } + + rxfifo_in = rxfifo_out = rxfifo_cnt = 0; + + return (0); +} + +void serial_putc(const char c) +{ + if (c == '\n') + max3100_putc('\r'); + + max3100_putc(c); +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc (*s++); +} + +int serial_getc(void) +{ + return max3100_getc(); +} + +int serial_tstc(void) +{ + return max3100_tstc(); +} + +/* XXX WTF? */ +void serial_setbrg(void) +{ +} + +#endif diff --git a/include/commproc.h b/include/commproc.h index f0ee1792b2..c10525d4e8 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -1191,7 +1191,12 @@ typedef struct scc_enet { #define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ #define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ -#define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 +# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ +#elif CONFIG_NETVIA_VERSION >= 2 +# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ +#endif + #define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 28ae9fa9e3..4e213dec78 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -38,9 +38,15 @@ #define CONFIG_NETVIA 1 /* ...on a NetVia board */ #undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */ +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE +#else +#define CONFIG_8xx_CONS_NONE +#define CONFIG_MAX3100_SERIAL +#endif + #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ #ifdef CONFIG_NETVIA_PLL_CLOCK @@ -76,17 +82,28 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ +#endif + #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP ) +#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING ) + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 +#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) +#else +#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE +#endif #define CONFIG_BOARD_PRE_INIT #define CONFIG_MISC_INIT_R @@ -168,10 +185,16 @@ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) +#define CFG_ENV_OFFSET 0 +#define CFG_ENV_SIZE 0x4000 + +#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000) +#define CFG_ENV_OFFSET_REDUND 0 +#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE + /*----------------------------------------------------------------------- * Cache Configuration */ @@ -276,22 +299,6 @@ #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V ) -/* - * BR1/2 and OR1/2 (4MByte Flash Bank x 2) - * - */ -#define FLASH0_SIZE 0x00400000 /* 4MByte */ -#define FLASH0_BASE 0xF0000000 - -#define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH0_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) -#define CFG_BR1_PRELIM ((FLASH0_BASE & BR_BA_MSK) | BR_PS_32 | BR_V) - -#define FLASH1_SIZE 0x00400000 -#define FLASH1_BASE 0xF0400000 - -#define CFG_OR2_PRELIM ((0xFFFFFFFFLU & ~(FLASH1_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) -#define CFG_BR2_PRELIM ((FLASH1_BASE & BR_BA_MSK) | BR_PS_32 | BR_V) - /* * BR3 and OR3 (SDRAM) * @@ -305,16 +312,6 @@ #define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) -/* - * BR6 (External register) - * 16 bit port size - leds are at high 8 bits - */ -#define EXTREG_BASE 0x30000000 /* external register */ -#define EXTREG_SIZE 0x00010000 /* max 64K */ - -#define CFG_OR6_PRELIM ((0xFFFFFFFFLU & ~(EXTREG_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX) -#define CFG_BR6_PRELIM ((EXTREG_BASE & BR_BA_MSK) | BR_PS_32 | BR_V) - /* * Memory Periodic Timer Prescaler */ @@ -347,4 +344,183 @@ #define CONFIG_ARTOS /* include ARTOS support */ +/****************************************************************/ + +#define DSP_SIZE 0x00010000 /* 64K */ +#define FPGA_SIZE 0x00010000 /* 64K */ + +#define DSP0_BASE 0xF1000000 +#define DSP1_BASE (DSP0_BASE + DSP_SIZE) +#define FPGA_BASE (DSP1_BASE + DSP_SIZE) + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +#define ER_SIZE 0x00010000 /* 64K */ +#define ER_BASE (FPGA_BASE + FPGA_SIZE) + +#define NAND_SIZE 0x00010000 /* 64K */ +#define NAND_BASE (ER_BASE + ER_SIZE) + +#endif + +/****************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +#define STATUS_LED_BIT 0x00000001 /* bit 31 */ +#define STATUS_LED_PERIOD (CFG_HZ / 2) +#define STATUS_LED_STATE STATUS_LED_BLINKING + +#define STATUS_LED_BIT1 0x00000002 /* bit 30 */ +#define STATUS_LED_PERIOD1 (CFG_HZ / 2) +#define STATUS_LED_STATE1 STATUS_LED_OFF + +#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ +#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ + +#endif + +/*****************************************************************************/ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +/* NAND */ +#define CFG_NAND_BASE NAND_BASE + +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +#define CFG_MAX_NAND_DEVICE 1 + +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 + +#define NAND_DISABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0040; \ + } while(0) + +#define NAND_ENABLE_CE(nand) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \ + } while(0) + +#define NAND_CTL_CLRALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \ + } while(0) + +#define NAND_CTL_SETALE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0100; \ + } while(0) + +#define NAND_CTL_CLRCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \ + } while(0) + +#define NAND_CTL_SETCLE(nandptr) \ + do { \ + (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |= 0x0080; \ + } while(0) + +#define NAND_WAIT_READY(nand) \ + do { \ + while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \ + ; \ + } while (0) + +#define WRITE_NAND_COMMAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND_ADDRESS(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define WRITE_NAND(d, adr) \ + do { \ + *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ + } while(0) + +#define READ_NAND(adr) \ + ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) + +#endif + +/*****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 + +/* LEDs */ + +/* last value written to the external register; we cannot read back */ +extern unsigned int last_er_val; + +/* led_id_t is unsigned long mask */ +typedef unsigned int led_id_t; + +static inline void __led_init(led_id_t mask, int state) +{ + unsigned int new_er_val; + + if (state) + new_er_val = last_er_val & ~mask; + else + new_er_val = last_er_val | mask; + + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +static inline void __led_toggle(led_id_t mask) +{ + unsigned int new_er_val; + + new_er_val = last_er_val ^ mask; + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +static inline void __led_set(led_id_t mask, int state) +{ + unsigned int new_er_val; + + if (state) + new_er_val = last_er_val & ~mask; + else + new_er_val = last_er_val | mask; + + *(volatile unsigned int *)ER_BASE = new_er_val; + last_er_val = new_er_val; +} + +/* MAX3100 console */ +#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_RXD_BIT 0x00000008 + +#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_TXD_BIT 0x00000004 + +#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) +#define MAX3100_SPI_CLK_BIT 0x00000002 + +#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) +#define MAX3100_CS_BIT 0x0010 + +#endif + +#endif + +/****************************************************************/ + #endif /* __CONFIG_H */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 2806b6dd0f..a257b82eb3 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -63,17 +63,17 @@ #define CONFIG_BAUDRATE 19200 #undef CONFIG_MISC_INIT_R /* not used yet */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include #define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=dhcp root=/dev/nfs, ether=0,0x08000000,eth0" +#define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.1.56 -#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_SERVERIP 192.168.1.5 #define CONFIG_BOOTCOMMAND "bootm 0x40000" #define CONFIG_SHOW_BOOT_PROGRESS @@ -125,6 +125,13 @@ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * Network chip + */ +#define CONFIG_DRIVER_CS8900 1 +#define CS8900_BUS32 1 +#define CS8900_BASE 0x08000000 + /* * Stack sizes * @@ -151,25 +158,276 @@ #define CFG_FLASH_BASE PHYS_FLASH_1 +# if 0 +/* FIXME: switch to _documented_ registers */ /* * GPIO settings + * + * GP15 == nCS1 is 1 + * GP24 == SFRM is 1 + * GP25 == TXD is 1 + * GP33 == nCS5 is 1 + * GP39 == FFTXD is 1 + * GP41 == RTS is 1 + * GP47 == TXD is 1 + * GP49 == nPWE is 1 + * GP62 == LED_B is 1 + * GP63 == TDM_OE is 1 + * GP78 == nCS2 is 1 + * GP79 == nCS3 is 1 + * GP80 == nCS4 is 1 + */ +#define CFG_GPSR0_VAL 0x03008000 +#define CFG_GPSR1_VAL 0xC0028282 +#define CFG_GPSR2_VAL 0x0001C000 + +/* GP02 == DON_RST is 0 + * GP23 == SCLK is 0 + * GP45 == USB_ACT is 0 + * GP60 == PLLEN is 0 + * GP61 == LED_A is 0 + * GP73 == SWUPD_LED is 0 + */ +#define CFG_GPCR0_VAL 0x00800004 +#define CFG_GPCR1_VAL 0x30002000 +#define CFG_GPCR2_VAL 0x00000100 + +/* GP00 == DON_READY is input + * GP01 == DON_OK is input + * GP02 == DON_RST is output + * GP03 == RESET_IND is input + * GP07 == RES11 is input + * GP09 == RES12 is input + * GP11 == SWUPDATE is input + * GP14 == nPOWEROK is input + * GP15 == nCS1 is output + * GP17 == RES22 is input + * GP18 == RDY is input + * GP23 == SCLK is output + * GP24 == SFRM is output + * GP25 == TXD is output + * GP26 == RXD is input + * GP32 == RES21 is input + * GP33 == nCS5 is output + * GP34 == FFRXD is input + * GP35 == CTS is input + * GP39 == FFTXD is output + * GP41 == RTS is output + * GP42 == USB_OK is input + * GP45 == USB_ACT is output + * GP46 == RXD is input + * GP47 == TXD is output + * GP49 == nPWE is output + * GP58 == nCPUBUSINT is input + * GP59 == LANINT is input + * GP60 == PLLEN is output + * GP61 == LED_A is output + * GP62 == LED_B is output + * GP63 == TDM_OE is output + * GP64 == nDSPINT is input + * GP65 == STRAP0 is input + * GP67 == STRAP1 is input + * GP69 == STRAP2 is input + * GP70 == STRAP3 is input + * GP71 == STRAP4 is input + * GP73 == SWUPD_LED is output + * GP78 == nCS2 is output + * GP79 == nCS3 is output + * GP80 == nCS4 is output + */ +#define CFG_GPDR0_VAL 0x03808004 +#define CFG_GPDR1_VAL 0xF002A282 +#define CFG_GPDR2_VAL 0x0001C200 + +/* GP15 == nCS1 is AF10 + * GP18 == RDY is AF01 + * GP23 == SCLK is AF10 + * GP24 == SFRM is AF10 + * GP25 == TXD is AF10 + * GP26 == RXD is AF01 + * GP33 == nCS5 is AF10 + * GP34 == FFRXD is AF01 + * GP35 == CTS is AF01 + * GP39 == FFTXD is AF10 + * GP41 == RTS is AF10 + * GP46 == RXD is AF10 + * GP47 == TXD is AF01 + * GP49 == nPWE is AF10 + * GP78 == nCS2 is AF10 + * GP79 == nCS3 is AF10 + * GP80 == nCS4 is AF10 */ -#define CFG_GPSR0_VAL 0xFFFFFFFF -#define CFG_GPSR1_VAL 0xFFFFFFFF -#define CFG_GPSR2_VAL 0xFFFFFFFF -#define CFG_GPCR0_VAL 0x08022080 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0xCD82A878 -#define CFG_GPDR1_VAL 0xFCFFAB80 -#define CFG_GPDR2_VAL 0x0001FFFF #define CFG_GAFR0_L_VAL 0x80000000 -#define CFG_GAFR0_U_VAL 0xA5254010 -#define CFG_GAFR1_L_VAL 0x599A9550 -#define CFG_GAFR1_U_VAL 0xAAA5AAAA -#define CFG_GAFR2_L_VAL 0xAAAAAAAA +#define CFG_GAFR0_U_VAL 0x001A8010 +#define CFG_GAFR1_L_VAL 0x60088058 +#define CFG_GAFR1_U_VAL 0x00000008 +#define CFG_GAFR2_L_VAL 0xA0000000 #define CFG_GAFR2_U_VAL 0x00000002 + +/* FIXME: set GPIO_RER/FER */ + +/* RDH = 1 + * PH = 1 + * VFS = 1 + * BFS = 1 + * SSS = 1 + */ +#define CFG_PSSR_VAL 0x37 + +/* + * Memory settings + * + * This is the configuration for nCS0/1 -> flash banks + * configuration for nCS1: + * [31] 0 - Slower Device + * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [19] 1 - 16 Bit bus width + * [18:16] 000 - nonburst RAM or FLASH + * configuration for nCS0: + * [15] 0 - Slower Device + * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns + * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns + * [03] 1 - 16 Bit bus width + * [02:00] 000 - nonburst RAM or FLASH + */ +#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ + +/* This is the configuration for nCS2/3 -> TDM-Switch, DSP + * configuration for nCS3: DSP + * [31] 0 - Slower Device + * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS2: TDM-Switch + * [15] 0 - Slower Device + * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns + * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns + * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC1_VAL 0x123C593C /* TDM switch, DSP */ + +/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller + * + * configuration for nCS5: LAN Controller + * [31] 0 - Slower Device + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns + * [19] 1 - 16 Bit bus width + * [18:16] 100 - variable latency I/O + * configuration for nCS4: ExtBus + * [15] 0 - Slower Device + * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns + * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns + * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns + * [03] 1 - 16 Bit bus width + * [02:00] 100 - variable latency I/O + */ +#define CFG_MSC2_VAL 0x123C6CDC /* extra bus, LAN controller */ + +/* MDCNFG: SDRAM Configuration Register + * + * [31:29] 000 - reserved + * [28] 0 - no SA1111 compatiblity mode + * [27] 0 - latch return data with return clock + * [26] 0 - alternate addressing for pair 2/3 + * [25:24] 00 - timings + * [23] 0 - internal banks in lower partition 2/3 (not used) + * [22:21] 00 - row address bits for partition 2/3 (not used) + * [20:19] 00 - column address bits for partition 2/3 (not used) + * [18] 0 - SDRAM partition 2/3 width is 32 bit + * [17] 0 - SDRAM partition 3 disabled + * [16] 0 - SDRAM partition 2 disabled + * [15:13] 000 - reserved + * [12] 1 - SA1111 compatiblity mode + * [11] 1 - latch return data with return clock + * [10] 0 - no alternate addressing for pair 0/1 + * [09:08] 01 - tRP=2*MemClk CL=2 tRCD=2*MemClk tRAS=5*MemClk tRC=8*MemClk + * [7] 1 - 4 internal banks in lower partition pair + * [06:05] 10 - 13 row address bits for partition 0/1 + * [04:03] 01 - 9 column address bits for partition 0/1 + * [02] 0 - SDRAM partition 0/1 width is 32 bit + * [01] 0 - disable SDRAM partition 1 + * [00] 1 - enable SDRAM partition 0 + */ +/* use the configuration above but disable partition 0 */ +#define CFG_MDCNFG_VAL 0x000019c8 + +/* MDREFR: SDRAM Refresh Control Register + * + * [32:26] 0 - reserved + * [25] 0 - K2FREE: not free running + * [24] 0 - K1FREE: not free running + * [23] 1 - K0FREE: not free running + * [22] 0 - SLFRSH: self refresh disabled + * [21] 0 - reserved + * [20] 0 - APD: no auto power down + * [19] 0 - K2DB2: SDCLK2 is MemClk + * [18] 0 - K2RUN: disable SDCLK2 + * [17] 0 - K1DB2: SDCLK1 is MemClk + * [16] 1 - K1RUN: enable SDCLK1 + * [15] 1 - E1PIN: SDRAM clock enable + * [14] 1 - K0DB2: SDCLK0 is MemClk + * [13] 0 - K0RUN: disable SDCLK0 + * [12] 1 - E0PIN: disable SDCKE0 + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 + */ +#define CFG_MDREFR_VAL 0x0081D018 + +/* MDMRS: Mode Register Set Configuration Register + * + * [31] 0 - reserved + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) + * [15] 0 - reserved + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. + */ +#define CFG_MDMRS_VAL 0x00020022 + +/* + * PCMCIA and CF Interfaces + */ +#define CFG_MECR_VAL 0x00000000 +#define CFG_MCMEM0_VAL 0x00000000 +#define CFG_MCMEM1_VAL 0x00000000 +#define CFG_MCATT0_VAL 0x00000000 +#define CFG_MCATT1_VAL 0x00000000 +#define CFG_MCIO0_VAL 0x00000000 +#define CFG_MCIO1_VAL 0x00000000 +#endif + +/* + * GPIO settings + */ +#define CFG_GPSR0_VAL 0xFFFFFFFF +#define CFG_GPSR1_VAL 0xFFFFFFFF +#define CFG_GPSR2_VAL 0xFFFFFFFF +#define CFG_GPCR0_VAL 0x08022080 +#define CFG_GPCR1_VAL 0x00000000 +#define CFG_GPCR2_VAL 0x00000000 +#define CFG_GPDR0_VAL 0xCD82A878 +#define CFG_GPDR1_VAL 0xFCFFAB80 +#define CFG_GPDR2_VAL 0x0001FFFF +#define CFG_GAFR0_L_VAL 0x80000000 +#define CFG_GAFR0_U_VAL 0xA5254010 +#define CFG_GAFR1_L_VAL 0x599A9550 +#define CFG_GAFR1_U_VAL 0xAAA5AAAA +#define CFG_GAFR2_L_VAL 0xAAAAAAAA +#define CFG_GAFR2_U_VAL 0x00000002 + /* FIXME: set GPIO_RER/FER */ #define CFG_PSSR_VAL 0x20 @@ -177,12 +435,13 @@ /* * Memory settings */ -#define CFG_MSC0_VAL 0x2EF025D0 -#define CFG_MSC1_VAL 0x00003F64 -#define CFG_MSC2_VAL 0x00000000 -#define CFG_MDCNFG_VAL 0x09a909a9 -#define CFG_MDREFR_VAL 0x03ca0030 -#define CFG_MDMRS_VAL 0x00220022 + +#define CFG_MSC0_VAL 0x2ef15af0 +#define CFG_MSC1_VAL 0x00003ff4 +#define CFG_MSC2_VAL 0x7ff07ff0 +#define CFG_MDCNFG_VAL 0x09a909a9 +#define CFG_MDREFR_VAL 0x038ff030 +#define CFG_MDMRS_VAL 0x00220022 /* * PCMCIA and CF Interfaces diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 312c854b67..60699fec45 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -30,8 +30,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define DEBUG 1 - /* * If we are developing, we might want to start U-Boot from ram * so we MUST NOT initialize critical regs like mem-timing ... @@ -62,7 +60,7 @@ #define CONFIG_BAUDRATE 19200 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP) +#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include diff --git a/include/configs/logodl.h b/include/configs/logodl.h index c018b6b646..cb737fc2da 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -58,8 +58,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_BAUDRATE 19200 -/*#define CONFIG_MISC_INIT_R 1 / * we have a misc_init_r() function */ -#undef CONFIG_MISC_INIT_R /* FIXME */ +#undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ #define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO) /* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ @@ -120,12 +119,14 @@ /* * SMSC91C111 Network Card */ -/*#define CONFIG_DRIVER_SMC91111 1 */ -/*#define CONFIG_SMC91111_BASE 0x10000000 / * chip select 4 */ -/*#undef CONFIG_SMC_USE_32_BIT / * 16 bit bus access */ -/*#undef CONFIG_SMC_91111_EXT_PHY / * we use internal phy */ -/*#undef CONFIG_SHOW_ACTIVITY */ -/*#define CONFIG_NET_RETRY_COUNT 10 / * # of retries */ +#if 0 +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */ +#undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ +#undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ +#undef CONFIG_SHOW_ACTIVITY +#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ +#endif /* * Stack sizes diff --git a/include/status_led.h b/include/status_led.h index 5a33e31e93..e8ba9fd42d 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -236,6 +236,8 @@ void status_led_set (int led, int state); /***** NetVia ********************************************************/ #elif defined(CONFIG_NETVIA) +#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 + #define STATUS_LED_PAR im_ioport.iop_pdpar #define STATUS_LED_DIR im_ioport.iop_pddir #undef STATUS_LED_ODR @@ -252,6 +254,7 @@ void status_led_set (int led, int state); # define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ +#endif /***** CMI ********************************************************/ #elif defined(CONFIG_CMI) diff --git a/include/version.h b/include/version.h index 8876686aa1..3f228c8b81 100644 --- a/include/version.h +++ b/include/version.h @@ -24,6 +24,6 @@ #ifndef __VERSION_H__ #define __VERSION_H__ -#define U_BOOT_VERSION "U-Boot 0.3.2" +#define U_BOOT_VERSION "U-Boot 0.4.0" #endif /* __VERSION_H__ */ diff --git a/rtc/ds12887.c b/rtc/ds12887.c index 5d9c5dd139..cf572ccdb4 100644 --- a/rtc/ds12887.c +++ b/rtc/ds12887.c @@ -45,7 +45,7 @@ #define RTC_CONTROL_C 0x0C #define RTC_CONTROL_D 0x0D -#define RTC_CA_UIP 0x80 +#define RTC_CA_UIP 0x80 #define RTC_CB_DM 0x04 #define RTC_CB_24_12 0x02 #define RTC_CB_SET 0x80 @@ -55,10 +55,10 @@ static uchar rtc_read (uchar reg) { uchar val; - + *(volatile unsigned char*)(RTC_PORT_ADDR) = reg; __asm__ __volatile__ ("sync"); - + val = *(volatile unsigned char*)(RTC_PORT_DATA); return (val); } @@ -95,7 +95,7 @@ void rtc_get (struct rtc_time *tmp) /* check if rtc is available for access */ while( rtc_read(RTC_CONTROL_A) & RTC_CA_UIP) ; - + sec = rtc_read(RTC_SECONDS); min = rtc_read(RTC_MINUTES); hour = rtc_read(RTC_HOURS); @@ -183,11 +183,11 @@ void rtc_set (struct rtc_time *tmp) min = tmp->tm_min; sec = tmp->tm_sec; } - + /* disables the RTC to update the regs */ save_ctrl_b = rtc_read(RTC_CONTROL_B); save_ctrl_b |= RTC_CB_SET; - rtc_write(RTC_CONTROL_B, save_ctrl_b); + rtc_write(RTC_CONTROL_B, save_ctrl_b); rtc_write (RTC_YEAR, year); rtc_write (RTC_MONTH, mon); @@ -199,24 +199,24 @@ void rtc_set (struct rtc_time *tmp) /* enables the RTC to update the regs */ save_ctrl_b &= ~RTC_CB_SET; - rtc_write(RTC_CONTROL_B, save_ctrl_b); + rtc_write(RTC_CONTROL_B, save_ctrl_b); } void rtc_reset (void) { struct rtc_time tmp; uchar ctrl_rg; - + ctrl_rg = RTC_CB_SET; - rtc_write(RTC_CONTROL_B,ctrl_rg); - + rtc_write(RTC_CONTROL_B,ctrl_rg); + tmp.tm_year = 1970 % 100; tmp.tm_mon = 1; tmp.tm_mday= 1; tmp.tm_hour = 0; tmp.tm_min = 0; tmp.tm_sec = 0; - + #ifdef RTC_DEBUG printf ( "RTC: %4d-%02d-%02d %2d:%02d:%02d UTC\n", tmp.tm_year, tmp.tm_mon, tmp.tm_mday, @@ -224,15 +224,15 @@ void rtc_reset (void) #endif ctrl_rg = RTC_CB_SET | RTC_CB_24_12 | RTC_CB_DM; - rtc_write(RTC_CONTROL_B,ctrl_rg); + rtc_write(RTC_CONTROL_B,ctrl_rg); rtc_set(&tmp); rtc_write(RTC_HOURS_ALARM, 0), - rtc_write(RTC_MINUTES_ALARM, 0), + rtc_write(RTC_MINUTES_ALARM, 0), rtc_write(RTC_SECONDS_ALARM, 0); - + ctrl_rg = RTC_CB_24_12 | RTC_CB_DM; - rtc_write(RTC_CONTROL_B,ctrl_rg); + rtc_write(RTC_CONTROL_B,ctrl_rg); } #endif /* (CONFIG_RTC_DS12887) && (CONFIG_COMMANDS & CFG_CMD_DATE) */ -- cgit v1.2.1