From 36f104e5caa747d568eff26b369565af57c2ffa6 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 23 Apr 2007 13:54:24 +0200 Subject: [patch] use unsigned char in smc91111 driver for mac the v_mac variable in the smc91111 driver is declared as a signed char ... this causes problems when one of the bytes in the MAC is "signed" like 0xE0 because when it gets printed out, you get a display like: 0xFFFFFFE0 and that's no good Signed-off-by: Mike Frysinger --- drivers/smc91111.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/smc91111.c b/drivers/smc91111.c index f91e4b9843..8061f12979 100644 --- a/drivers/smc91111.c +++ b/drivers/smc91111.c @@ -1538,9 +1538,9 @@ int eth_send(volatile void *packet, int length) { int smc_get_ethaddr (bd_t * bd) { int env_size, rom_valid, env_present = 0, reg; - char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; + char *s = NULL, *e, es[] = "11:22:33:44:55:66"; char s_env_mac[64]; - uchar v_env_mac[6], v_rom_mac[6]; + uchar v_env_mac[6], v_rom_mac[6], *v_mac; env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); if ((env_size > 0) && (env_size < sizeof (es))) { /* exit if env is bad */ @@ -1563,7 +1563,7 @@ int smc_get_ethaddr (bd_t * bd) if (!env_present) { /* if NO env */ if (rom_valid) { /* but ROM is valid */ - v_mac = (char *)v_rom_mac; + v_mac = v_rom_mac; sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0], v_mac[1], v_mac[2], v_mac[3], v_mac[4], v_mac[5]); @@ -1573,7 +1573,7 @@ int smc_get_ethaddr (bd_t * bd) return (-1); } } else { /* good env, don't care ROM */ - v_mac = (char *)v_env_mac; /* always use a good env over a ROM */ + v_mac = v_env_mac; /* always use a good env over a ROM */ } if (env_present && rom_valid) { /* if both env and ROM are good */ -- cgit v1.2.1 From afb903a2eb9436baa9270ccc0c27082d86497d89 Mon Sep 17 00:00:00 2001 From: Jeffrey Mann Date: Mon, 23 Apr 2007 14:00:11 +0200 Subject: [patch] setenv(...) can delete environmentalvariables update setenv() function so that entering a NULL value for the variable's value will delete the environmental variable Signed-off-by: Jeffrey Mann Acked-by: Stefan Roese --- common/cmd_nvedit.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) mode change 100644 => 100755 common/cmd_nvedit.c diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c old mode 100644 new mode 100755 index 9834ba65b7..977ec5bae9 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -391,7 +391,10 @@ int _do_setenv (int flag, int argc, char *argv[]) void setenv (char *varname, char *varvalue) { char *argv[4] = { "setenv", varname, varvalue, NULL }; - _do_setenv (0, 3, argv); + if (varvalue == NULL) + _do_setenv (0, 2, argv); + else + _do_setenv (0, 3, argv); } int do_setenv ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -- cgit v1.2.1 From 38257988abfe74d459ca2ad748b109ca04e4efe1 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 23 Apr 2007 15:30:39 +0200 Subject: [PATCH] Avoid assigning PCI resources from zero address If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE core complains and IDE drivers fails to work. Also, assigning zero to a BAR was illegal according to PCI 2.1 (the later revisions seem to have excluded the sentence about "0" being considered an invalid address) -- so, use a reasonable starting value of 0x1000 (that's what the most Linux archs are using). Alternatively, one might have fixed the calls to pci_set_region() individually (some code even seems to have taken care of this issue) but that would have been a lot more work. :-) Signed-off-by: Sergei Shtylyov Acked-by: Stefan Roese --- drivers/pci_auto.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 969167555e..f170c2db89 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -34,7 +34,12 @@ void pciauto_region_init(struct pci_region* res) { - res->bus_lower = res->bus_start; + /* + * Avoid allocating PCI resources from address 0 -- this is illegal + * according to PCI 2.1 and moreover, this is known to cause Linux IDE + * drivers to fail. Use a reasonable starting value of 0x1000 instead. + */ + res->bus_lower = res->bus_start ? res->bus_start : 0x1000; } void pciauto_region_align(struct pci_region *res, unsigned long size) -- cgit v1.2.1 From 7fc4c71a143be8666d70803fb25ae60379c95622 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 23 Apr 2007 15:39:59 +0200 Subject: Fix file mode Signed-off-by: Stefan Roese --- common/cmd_nvedit.c | 0 1 file changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 common/cmd_nvedit.c diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c old mode 100755 new mode 100644 -- cgit v1.2.1 From ada4d40091f6ed4a4f0040e08d20db21967e4a67 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Wed, 25 Apr 2007 16:01:26 +0200 Subject: [PATCH] simplify silent console Signed-off-by: Ladislav Michl Acked-by: Stefan Roese --- common/console.c | 8 +------- common/main.c | 50 +++++++++++--------------------------------------- 2 files changed, 12 insertions(+), 46 deletions(-) diff --git a/common/console.c b/common/console.c index e9f23bec18..d8a0cb6c7e 100644 --- a/common/console.c +++ b/common/console.c @@ -494,13 +494,7 @@ int console_init_r (void) /* suppress all output if splash screen is enabled and we have a bmp to display */ if (getenv("splashimage") != NULL) - outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); -#endif - -#ifdef CONFIG_SILENT_CONSOLE - /* Suppress all output if "silent" mode requested */ - if (gd->flags & GD_FLG_SILENT) - outputdev = search_device (DEV_FLAGS_OUTPUT, "nulldev"); + gd->flags |= GD_FLG_SILENT; #endif /* Scan devices looking for input and output devices */ diff --git a/common/main.c b/common/main.c index cc4b50f615..0003da2511 100644 --- a/common/main.c +++ b/common/main.c @@ -112,16 +112,8 @@ static __inline__ int abortboot(int bootdelay) u_int presskey_max = 0; u_int i; -#ifdef CONFIG_SILENT_CONSOLE - if (gd->flags & GD_FLG_SILENT) { - /* Restore serial console */ - console_assign (stdout, "serial"); - console_assign (stderr, "serial"); - } -#endif - # ifdef CONFIG_AUTOBOOT_PROMPT - printf (CONFIG_AUTOBOOT_PROMPT, bootdelay); + printf(CONFIG_AUTOBOOT_PROMPT, bootdelay); # endif # ifdef CONFIG_AUTOBOOT_DELAY_STR @@ -195,18 +187,12 @@ static __inline__ int abortboot(int bootdelay) } # if DEBUG_BOOTKEYS if (!abort) - puts ("key timeout\n"); + puts("key timeout\n"); # endif #ifdef CONFIG_SILENT_CONSOLE - if (abort) { - /* permanently enable normal console output */ - gd->flags &= ~(GD_FLG_SILENT); - } else if (gd->flags & GD_FLG_SILENT) { - /* Restore silent console */ - console_assign (stdout, "nulldev"); - console_assign (stderr, "nulldev"); - } + if (abort) + gd->flags &= ~GD_FLG_SILENT; #endif return abort; @@ -222,14 +208,6 @@ static __inline__ int abortboot(int bootdelay) { int abort = 0; -#ifdef CONFIG_SILENT_CONSOLE - if (gd->flags & GD_FLG_SILENT) { - /* Restore serial console */ - console_assign (stdout, "serial"); - console_assign (stderr, "serial"); - } -#endif - #ifdef CONFIG_MENUPROMPT printf(CONFIG_MENUPROMPT, bootdelay); #else @@ -244,8 +222,8 @@ static __inline__ int abortboot(int bootdelay) if (bootdelay >= 0) { if (tstc()) { /* we got a key press */ (void) getc(); /* consume input */ - puts ("\b\b\b 0"); - abort = 1; /* don't auto boot */ + puts("\b\b\b 0"); + abort = 1; /* don't auto boot */ } } #endif @@ -266,23 +244,17 @@ static __inline__ int abortboot(int bootdelay) # endif break; } - udelay (10000); + udelay(10000); } - printf ("\b\b\b%2d ", bootdelay); + printf("\b\b\b%2d ", bootdelay); } - putc ('\n'); + putc('\n'); #ifdef CONFIG_SILENT_CONSOLE - if (abort) { - /* permanently enable normal console output */ - gd->flags &= ~(GD_FLG_SILENT); - } else if (gd->flags & GD_FLG_SILENT) { - /* Restore silent console */ - console_assign (stdout, "nulldev"); - console_assign (stderr, "nulldev"); - } + if (abort) + gd->flags &= ~GD_FLG_SILENT; #endif return abort; -- cgit v1.2.1 From 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- cpu/mpc5xxx/cpu.c | 12 ++++++++---- include/asm-ppc/processor.h | 8 ++++++-- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 813aa7935d..73b166d999 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -53,12 +53,16 @@ int checkcpu (void) #else svr = get_svr(); pvr = get_pvr(); - switch (SVR_VER (svr)) { - case SVR_MPC5200: - printf ("MPC5200"); + + switch (pvr) { + case PVR_5200: + printf("MPC5200"); + break; + case PVR_5200B: + printf("MPC5200B"); break; default: - printf ("MPC52?? (SVR %08x)", svr); + printf("Unknown MPC5xxx"); break; } diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 058596275f..7c11c9e023 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -701,8 +701,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +811,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register -- cgit v1.2.1 From 2f550ab976405300f5b07bf2890800840d0aa05f Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Sat, 5 May 2007 08:12:30 +0200 Subject: 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi Acked-by: Grant Likely --- cpu/mpc5xxx/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 73b166d999..1eac2bbfbe 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -131,5 +131,9 @@ ft_cpu_setup(void *blob, bd_t *bd) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); + + p = ft_get_prop(blob, "/" OF_SOC "/ethernet@3000/local-mac-address", &len); + if (p != NULL) + memcpy(p, bd->bi_enetaddr, 6); } #endif -- cgit v1.2.1 From 56fd7162985c412317bbf763a225fba23c64fd31 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Tue, 15 May 2007 07:55:42 -0700 Subject: Fix for compile of JSE target The attached patch fixes the compile of the JSE board in the denx git as of 14 may 2007. It is an extremely simple patch, it just adds the missing define of CFG_SYSTEMACE_WIDTH. Fix to compile JSE against 20070514 git of u-boot --- include/configs/JSE.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/JSE.h b/include/configs/JSE.h index ccd1f19903..7fa9ed2d42 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -49,6 +49,7 @@ /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ #define CONFIG_SYSTEMACE 1 #define CFG_SYSTEMACE_BASE 0xf0000000 +#define CFG_SYSTEMACE_WIDTH 8 #define CONFIG_DOS_PARTITION 1 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -- cgit v1.2.1 From 5dfaa50eb819686bfba1927e8c5b8a70a4d65fd3 Mon Sep 17 00:00:00 2001 From: "Aubrey.Li" Date: Mon, 14 May 2007 11:47:35 +0800 Subject: Fix compilation issues on MACOSX Singed-off-by: Marc Hoffman Signed-off-by: Aubrey Li --- tools/Makefile | 2 +- tools/mkimage.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 6177f90271..5e26bd7dd5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -74,7 +74,7 @@ TOOLSUBDIRS = ifeq ($(HOSTOS)-$(HOSTARCH),darwin-ppc) HOST_CFLAGS = -traditional-cpp -Wall HOST_LDFLAGS =-multiply_defined suppress -HOST_ENVIRO_CFLAGS = -traditional-cpp +HOST_ENVIRO_CFLAGS = else ifeq ($(HOSTOS)-$(HOSTARCH),netbsd-ppc) diff --git a/tools/mkimage.c b/tools/mkimage.c index 416e658f7c..21251306ac 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -446,7 +446,7 @@ NXTARG: ; } /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); @@ -496,7 +496,7 @@ NXTARG: ; (void) munmap((void *)ptr, sbuf.st_size); /* We're a bit of paranoid */ -#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) +#if defined(_POSIX_SYNCHRONIZED_IO) && !defined(__sun__) && !defined(__FreeBSD__) && !defined(__APPLE__) (void) fdatasync (ifd); #else (void) fsync (ifd); -- cgit v1.2.1 From 1b305bdc754c8468e1d5d858f5dcf8a7a0a4bb7a Mon Sep 17 00:00:00 2001 From: Zang Roy-r61911 Date: Wed, 9 May 2007 08:10:57 +0800 Subject: Search the exception table with linear algorithm Search the exception table with linear algorithm instead of bisecting algorithm. Because the exception table might be unsorted. Signed-off-by: Roy Zang --- lib_ppc/extable.c | 39 ++++++++++++++++++--------------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index b14d661bbe..8354411f01 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -52,30 +52,27 @@ search_one_table(const struct exception_table_entry *first, const struct exception_table_entry *last, unsigned long value) { - while (first <= last) { - const struct exception_table_entry *mid; - long diff; - - mid = (last - first) / 2 + first; - if ((ulong) mid > CFG_MONITOR_BASE) { - /* exception occurs in FLASH, before u-boot relocation. - * No relocation offset is needed. - */ - diff = mid->insn - value; + long diff; + if ((ulong) first > CFG_MONITOR_BASE) { + /* exception occurs in FLASH, before u-boot relocation. + * No relocation offset is needed. + */ + while (first <= last) { + diff = first->insn - value; if (diff == 0) - return mid->fixup; - } else { - /* exception occurs in RAM, after u-boot relocation. - * A relocation offset should be added. - */ - diff = (mid->insn + gd->reloc_off) - value; + return first->fixup; + first++; + } + } else { + /* exception occurs in RAM, after u-boot relocation. + * A relocation offset should be added. + */ + while (first <= last) { + diff = (first->insn + gd->reloc_off) - value; if (diff == 0) - return (mid->fixup + gd->reloc_off); + return (first->fixup + gd->reloc_off); + first++; } - if (diff < 0) - first = mid + 1; - else - last = mid - 1; } return 0; } -- cgit v1.2.1 From c3243cf7b490057277d61acffe4ad0946f9eb4a4 Mon Sep 17 00:00:00 2001 From: Joe Hamman Date: Mon, 30 Apr 2007 16:47:28 -0500 Subject: Add support for BCM5464 Quad Phy Added support for Broadcom's BCM5464 Quad Phy Signed-off-by: Joe Hamman --- drivers/tsec.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/tsec.c b/drivers/tsec.c index b4187739cb..790ba47c78 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -928,6 +928,33 @@ struct phy_info phy_info_BCM5461S = { }, }; +struct phy_info phy_info_BCM5464S = { + 0x02060b1, /* 5464 ID */ + "Broadcom BCM5464S", + 0, /* not clear to me what minor revisions we can shift away */ + (struct phy_cmd[]) { /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]) { /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr}, + {miim_end,} + }, + (struct phy_cmd[]) { /* shutdown */ + {miim_end,} + }, +}; + struct phy_info phy_info_M88E1011S = { 0x01410c6, "Marvell 88E1011S", @@ -1292,6 +1319,7 @@ struct phy_info *phy_info[] = { &phy_info_cis8204, &phy_info_cis8201, &phy_info_BCM5461S, + &phy_info_BCM5464S, &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, -- cgit v1.2.1 From 644e6fb4eb8be90ea04ba34b643a8bf019d680e0 Mon Sep 17 00:00:00 2001 From: mushtaq khan Date: Mon, 30 Apr 2007 15:57:22 +0530 Subject: Fixes bug clearing the bss section for i386 Hi, There is a bug in the code of clearing the bss section for processor i386.(File: cpu/i386/start.S) In the code, bss_start addr (starting addr of bss section) is put into the register %eax, but the code which clears the bss section refers to the addr pointed by %edi. This patch fixes this bug by putting bss_start into %edi register. Signed-off-by: Mushtaq Khan --- cpu/i386/start.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/i386/start.S b/cpu/i386/start.S index afcbb24520..1a54dd10e3 100644 --- a/cpu/i386/start.S +++ b/cpu/i386/start.S @@ -149,7 +149,7 @@ data_ok: .progress3: /* clear bss section in ram, size must be 4-byte aligned */ - movl $_i386boot_bss_start, %eax /* BSS start */ + movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */ movl $_i386boot_bss_size, %ecx /* BSS size */ movl %ecx, %eax andl $3, %eax -- cgit v1.2.1 From 66d9dbec1cc27d6398ee6cf84639dbe14971251e Mon Sep 17 00:00:00 2001 From: mushtaq khan Date: Fri, 20 Apr 2007 14:23:02 +0530 Subject: Add driver for S-ATA-controller on Intel processors with South Bridge, ICH-5, ICH-6 and ICH-7. Implementation: 1. Code is divided in to two files. All functions, which are controller specific are kept in "drivers/ata_piix.c" file and functions, which are not controller specific, are kept in "common/cmd_sata.c" file. 2. Reading and Writing from the S-ATA drive is done using PIO method. 3. Driver can be configured for 48-bit addressing by defining macro CONFIG_LBA48, if this macro is not defined driver uses the 28-bit addressing. 4. S-ATA read function is hooked to the File system, commands like ext2ls and ext2load file can be used. This has been tested. 5. U-Boot command "SATA_init" is added, which initializes the S-ATA controller and identifies the S-ATA drives connected to it. 6. U-Boot command "sata" is added, which is used to read/write, print partition table and get info about the drives present. This I have implemented in same way as "ide" command is implemented in U-Boot. 7. This driver is for S-ATA in native mode. 8. This driver does not support the Native command queuing and Hot-plugging. Signed-off-by: Mushtaq Khan --- common/Makefile | 4 +- common/cmd_sata.c | 710 ++++++++++++++++++++++++++++++++++++++++++++ drivers/Makefile | 2 +- drivers/ata_piix.c | 216 ++++++++++++++ include/ata.h | 60 ++++ include/configs/sc520_cdp.h | 9 + include/sata.h | 108 +++++++ 7 files changed, 1106 insertions(+), 3 deletions(-) create mode 100644 common/cmd_sata.c create mode 100644 drivers/ata_piix.c create mode 100644 include/sata.h diff --git a/common/Makefile b/common/Makefile index 5dfd3a84a2..1e4ce312cd 100644 --- a/common/Makefile +++ b/common/Makefile @@ -38,8 +38,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \ - cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ - cmd_usb.o cmd_vfd.o \ + cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \ + cmd_universe.o cmd_usb.o cmd_vfd.o \ command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ environment.o env_common.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ diff --git a/common/cmd_sata.c b/common/cmd_sata.c new file mode 100644 index 0000000000..1c71b6471d --- /dev/null +++ b/common/cmd_sata.c @@ -0,0 +1,710 @@ +/* + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to libata in kernel 2.4.32 + * +*/ + +/*File contains SATA read-write and other utility functions.*/ +#include +#include +#include +#include +#include +#include +#include + +#ifdef CFG_SATA_SUPPORTED +/*For debug prints set macro DEBUG_SATA to 1 */ +#define DEBUG_SATA 0 +/*Macro for SATA library specific declarations */ +#define SATA_DECL +#include +#undef SATA_DECL + +static u8 __inline__ +sata_inb (unsigned long ioaddr) +{ + return inb (ioaddr); +} + +static void __inline__ +sata_outb (unsigned char val, unsigned long ioaddr) +{ + outb (val, ioaddr); +} + +static void +output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) +{ + outsw (ioaddr->data_addr, sect_buf, words << 1); +} + +static int +input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) +{ + insw (ioaddr->data_addr, sect_buf, words << 1); + return 0; +} + +static void +sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len) +{ + unsigned char *end, *last; + + last = dst; + end = src + len - 1; + + /* reserve space for '\0' */ + if (len < 2) + goto OUT; + + /* skip leading white space */ + while ((*src) && (src < end) && (*src == ' ')) + ++src; + + /* copy string, omitting trailing white space */ + while ((*src) && (src < end)) { + *dst++ = *src; + if (*src++ != ' ') + last = dst; + } + OUT: + *last = '\0'; +} + +int +sata_bus_softreset (int num) +{ + u8 dev = 0, status = 0, i; + + port[num].dev_mask = 0; + + for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) { + if (!(sata_devchk (&port[num].ioaddr, i))) { + PRINTF ("dev_chk failed for dev#%d\n", i); + } else { + port[num].dev_mask |= (1 << i); + PRINTF ("dev_chk passed for dev#%d\n", i); + } + } + + if (!(port[num].dev_mask)) { + printf ("no devices on port%d\n", num); + return 1; + } + + dev_select (&port[num].ioaddr, dev); + + port[num].ctl_reg = 0x08; /*Default value of control reg */ + sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + udelay (10); + sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); + udelay (10); + sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + + /* spec mandates ">= 2ms" before checking status. + * We wait 150ms, because that was the magic delay used for + * ATAPI devices in Hale Landis's ATADRVR, for the period of time + * between when the ATA command register is written, and then + * status is checked. Because waiting for "a while" before + * checking status is fine, post SRST, we perform this magic + * delay here as well. + */ + msleep (150); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300); + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3); + } + + if (status & ATA_BUSY) + printf ("ata%u is slow to respond,plz be patient\n", port); + + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_chk_status (&port[num].ioaddr); + } + + if (status & ATA_BUSY) { + printf ("ata%u failed to respond : ", port); + printf ("bus reset failed\n"); + return 1; + } + return 0; +} + +void +sata_identify (int num, int dev) +{ + u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev; + u16 iobuf[ATA_SECT_SIZE]; + u64 n_sectors = 0; + u8 mask = 0; + + memset (iobuf, 0, sizeof (iobuf)); + hd_driveid_t *iop = (hd_driveid_t *) iobuf; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + printf ("dev%d is not present on port#%d\n", dev, num); + return; + } + + printf ("port=%d dev=%d\n", num, dev); + + dev_select (&port[num].ioaddr, dev); + + status = 0; + cmd = ATA_CMD_IDENT; /*Device Identify Command */ + sata_outb (cmd, port[num].ioaddr.command_addr); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (10); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000); + if (status & ATA_ERR) { + printf ("\ndevice not responding\n"); + port[num].dev_mask &= ~mask; + return; + } + + input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS); + + PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x" + "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49], + iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86], + iobuf[87], iobuf[88]); + + /* we require LBA and DMA support (bits 8 & 9 of word 49) */ + if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) { + PRINTF ("ata%u: no dma/lba\n", num); + } + ata_dump_id (iobuf); + + if (ata_id_has_lba48 (iobuf)) { + n_sectors = ata_id_u64 (iobuf, 100); + } else { + n_sectors = ata_id_u32 (iobuf, 60); + } + PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100)); + PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60)); + + if (n_sectors == 0) { + port[num].dev_mask &= ~mask; + return; + } + + sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev, + sizeof (sata_dev_desc[devno].revision)); + sata_cpy (sata_dev_desc[devno].vendor, iop->model, + sizeof (sata_dev_desc[devno].vendor)); + sata_cpy (sata_dev_desc[devno].product, iop->serial_no, + sizeof (sata_dev_desc[devno].product)); + strswab (sata_dev_desc[devno].revision); + strswab (sata_dev_desc[devno].vendor); + + if ((iop->config & 0x0080) == 0x0080) { + sata_dev_desc[devno].removable = 1; + } else { + sata_dev_desc[devno].removable = 0; + } + + sata_dev_desc[devno].lba = iop->lba_capacity; + PRINTF ("lba=0x%x", sata_dev_desc[devno].lba); + +#ifdef CONFIG_LBA48 + if (iop->command_set_2 & 0x0400) { + sata_dev_desc[devno].lba48 = 1; + lba = (unsigned long long) iop->lba48_capacity[0] | + ((unsigned long long) iop->lba48_capacity[1] << 16) | + ((unsigned long long) iop->lba48_capacity[2] << 32) | + ((unsigned long long) iop->lba48_capacity[3] << 48); + } else { + sata_dev_desc[devno].lba48 = 0; + } +#endif + + /* assuming HD */ + sata_dev_desc[devno].type = DEV_TYPE_HARDDISK; + sata_dev_desc[devno].blksz = ATA_BLOCKSIZE; + sata_dev_desc[devno].lun = 0; /* just to fill something in... */ +} + +void +set_Feature_cmd (int num, int dev) +{ + u8 mask = 0x00, status = 0; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + PRINTF ("dev%d is not present on port#%d\n", dev, num); + return; + } + + dev_select (&port[num].ioaddr, dev); + + sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr); + sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr); + sata_outb (0, port[num].ioaddr.lbal_addr); + sata_outb (0, port[num].ioaddr.lbam_addr); + sata_outb (0, port[num].ioaddr.lbah_addr); + + sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr); + + udelay (50); + msleep (150); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000); + if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) { + printf ("Error : status 0x%02x\n", status); + port[num].dev_mask &= ~mask; + } +} + +void +sata_port (struct sata_ioports *ioport) +{ + ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA; + ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR; + ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE; + ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT; + ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL; + ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM; + ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH; + ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE; + ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS; + ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD; +} + +int +sata_devchk (struct sata_ioports *ioaddr, int dev) +{ + u8 nsect, lbal; + + dev_select (ioaddr, dev); + + sata_outb (0x55, ioaddr->nsect_addr); + sata_outb (0xaa, ioaddr->lbal_addr); + + sata_outb (0xaa, ioaddr->nsect_addr); + sata_outb (0x55, ioaddr->lbal_addr); + + sata_outb (0x55, ioaddr->nsect_addr); + sata_outb (0xaa, ioaddr->lbal_addr); + + nsect = sata_inb (ioaddr->nsect_addr); + lbal = sata_inb (ioaddr->lbal_addr); + + if ((nsect == 0x55) && (lbal == 0xaa)) + return 1; /* we found a device */ + else + return 0; /* nothing found */ +} + +void +dev_select (struct sata_ioports *ioaddr, int dev) +{ + u8 tmp = 0; + + if (dev == 0) + tmp = ATA_DEVICE_OBS; + else + tmp = ATA_DEVICE_OBS | ATA_DEV1; + + sata_outb (tmp, ioaddr->device_addr); + sata_inb (ioaddr->altstatus_addr); + udelay (5); +} + +u8 +sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max) +{ + u8 status; + + do { + udelay (1000); + status = sata_chk_status (ioaddr); + max--; + } while ((status & bits) && (max > 0)); + + return status; +} + +u8 +sata_chk_status (struct sata_ioports * ioaddr) +{ + return sata_inb (ioaddr->status_addr); +} + +void +msleep (int count) +{ + int i; + + for (i = 0; i < count; i++) + udelay (1000); +} + +ulong +sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +{ + ulong n = 0; + u8 dev = 0, num = 0, mask = 0, status = 0; + +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + if (!sata_dev_desc[devno].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + /*Port Number */ + num = device / CFG_SATA_DEVS_PER_BUS; + /*dev on the port */ + if (device >= CFG_SATA_DEVS_PER_BUS) + dev = device - CFG_SATA_DEVS_PER_BUS; + else + dev = device; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + printf ("dev%d is not present on port#%d\n", dev, num); + return 0; + } + + /* Select device */ + dev_select (&port[num].ioaddr, dev); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", port[num].port_no); + return n; + } + while (blkcnt-- > 0) { + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", 0); + return n; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + sata_outb (0, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 24) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 32) & 0xFF, + port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 40) & 0xFF, + port[num].ioaddr.lbah_addr); + } +#endif + sata_outb (1, port[num].ioaddr.nsect_addr); + sata_outb (((blknr) >> 0) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); + +#ifdef CONFIG_LBA48 + if (lba48) { + sata_outb (ATA_LBA, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_READ_EXT, + port[num].ioaddr.command_addr); + } else +#endif + { + sata_outb (ATA_LBA | ((blknr >> 24) & 0xF), + port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_READ, + port[num].ioaddr.command_addr); + } + + msleep (50); + /*may take up to 4 sec */ + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000); + + if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) + != ATA_STAT_DRQ) { + u8 err = 0; + + printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n", + device, (ulong) blknr, status); + err = sata_inb (port[num].ioaddr.error_addr); + printf ("Error reg = 0x%x\n", err); + return (n); + } + input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (50); + + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } + return n; +} + +ulong +sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +{ + ulong n = 0; + unsigned char status = 0, num = 0, dev = 0, mask = 0; + +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + if (!sata_dev_desc[devno].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + /*Port Number */ + num = device / CFG_SATA_DEVS_PER_BUS; + /*dev on the Port */ + if (device >= CFG_SATA_DEVS_PER_BUS) + dev = device - CFG_SATA_DEVS_PER_BUS; + else + dev = device; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + /* Select device */ + dev_select (&port[num].ioaddr, dev); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", port[num].port_no); + return n; + } + + while (blkcnt-- > 0) { + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", + port[num].port_no); + return n; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + sata_outb (0, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 24) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 32) & 0xFF, + port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 40) & 0xFF, + port[num].ioaddr.lbah_addr); + } +#endif + sata_outb (1, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); +#ifdef CONFIG_LBA48 + if (lba48) { + sata_outb (ATA_LBA, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_WRITE_EXT, + port[num].ioaddr.command_addr); + } else +#endif + { + sata_outb (ATA_LBA | ((blknr >> 24) & 0xF), + port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_WRITE, + port[num].ioaddr.command_addr); + } + + msleep (50); + /*may take up to 4 sec */ + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000); + if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) + != ATA_STAT_DRQ) { + printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n", + device, (ulong) blknr, status); + return (n); + } + + output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (50); + + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } + return n; +} + +block_dev_desc_t *sata_get_dev (int dev); + +block_dev_desc_t * +sata_get_dev (int dev) +{ + return ((block_dev_desc_t *) & sata_dev_desc[dev]); +} + +int +do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp (argv[1], "init", 4) == 0) { + int rcode = 0; + + rcode = init_sata (); + if (rcode) + printf ("Sata initialization Failed\n"); + return rcode; + } else if (strncmp (argv[1], "inf", 3) == 0) { + int i; + + putc ('\n'); + for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) { + /*List only known devices */ + if (sata_dev_desc[i].type == + DEV_TYPE_UNKNOWN) + continue; + printf ("sata dev %d: ", i); + dev_print (&sata_dev_desc[i]); + } + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp (argv[1], "dev") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); + + if (dev >= CFG_SATA_MAXDEVICES) { + printf ("\nSata dev %d not available\n", + dev); + return 1; + } + printf ("\nSATA dev %d: ", dev); + dev_print (&sata_dev_desc[dev]); + if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN) + return 1; + curr_dev = dev; + return 0; + } else if (strcmp (argv[1], "part") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); + + if (dev >= CFG_SATA_MAXDEVICES) { + printf ("\nSata dev %d not available\n", + dev); + return 1; + } + PRINTF ("\nSATA dev %d: ", dev); + if (sata_dev_desc[dev].part_type != + PART_TYPE_UNKNOWN) { + print_part (&sata_dev_desc[dev]); + } else { + printf ("\nSata dev %d partition type " + "unknown\n", dev); + return 1; + } + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + if (argc < 5) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + if (strcmp (argv[1], "read") == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong cnt = simple_strtoul (argv[4], NULL, 16); + ulong n; + lbaint_t blk = simple_strtoul (argv[3], NULL, 16); + + memset ((int *) addr, 0, cnt * 512); + printf ("\nSATA read: dev %d blk # %ld," + "count %ld ... ", curr_dev, blk, cnt); + n = sata_read (curr_dev, blk, cnt, (ulong *) addr); + /* flush cache after read */ + flush_cache (addr, cnt * 512); + printf ("%ld blocks read: %s\n", n, + (n == cnt) ? "OK" : "ERR"); + if (n == cnt) + return 1; + else + return 0; + } else if (strcmp (argv[1], "write") == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong cnt = simple_strtoul (argv[4], NULL, 16); + ulong n; + lbaint_t blk = simple_strtoul (argv[3], NULL, 16); + + printf ("\nSata write: dev %d blk # %ld," + "count %ld ... ", curr_dev, blk, cnt); + n = sata_write (curr_dev, blk, cnt, (ulong *) addr); + printf ("%ld blocks written: %s\n", n, + (n == cnt) ? "OK" : "ERR"); + if (n == cnt) + return 1; + else + return 0; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } /*End OF SWITCH */ +} + +U_BOOT_CMD (sata, 5, 1, do_sata, + "sata init\n" + "sata info\n" + "sata part device\n" + "sata dev device\n" + "sata read addr blk# cnt\n" + "sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n"); + +#endif diff --git a/drivers/Makefile b/drivers/Makefile index d68cba682b..8ad530fb2a 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c new file mode 100644 index 0000000000..7e611633be --- /dev/null +++ b/drivers/ata_piix.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to ata_piix driver in kernel 2.4.32 +*/ + +/* +This file contains SATA controller and SATA drive initialization functions +*/ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CFG_ATA_PIIX /*ata_piix driver */ + +#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ + +#define DRV_DECL /*For file specific declarations */ +#include +#undef DRV_DECL + +/*Macros realted to PCI*/ +#define PCI_SATA_BUS 0x00 +#define PCI_SATA_DEV 0x1f +#define PCI_SATA_FUNC 0x02 + +#define PCI_SATA_BASE1 0x10 +#define PCI_SATA_BASE2 0x14 +#define PCI_SATA_BASE3 0x18 +#define PCI_SATA_BASE4 0x1c +#define PCI_SATA_BASE5 0x20 +#define PCI_PMR 0x90 +#define PCI_PI 0x09 +#define PCI_PCS 0x92 +#define PCI_DMA_CTL 0x48 + +#define PORT_PRESENT (1<<0) +#define PORT_ENABLED (1<<4) + +u32 bdf; +u32 iobase1 = 0; /*Primary cmd block */ +u32 iobase2 = 0; /*Primary ctl block */ +u32 iobase3 = 0; /*Sec cmd block */ +u32 iobase4 = 0; /*sec ctl block */ +u32 iobase5 = 0; /*BMDMA*/ +int +pci_sata_init (void) +{ + u32 bus = PCI_SATA_BUS; + u32 dev = PCI_SATA_DEV; + u32 fun = PCI_SATA_FUNC; + u16 cmd = 0; + u8 lat = 0, pcibios_max_latency = 0xff; + u8 pmr; /*Port mapping reg */ + u8 pi; /*Prgming Interface reg */ + + bdf = PCI_BDF (bus, dev, fun); + pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1); + pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2); + pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3); + pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4); + pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5); + + if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) || + (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) || + (iobase5 == 0xFFFFFFFF)) { + printf ("error no base addr for SATA controller\n"); + return 1; + /*ERROR*/} + + iobase1 &= 0xFFFFFFFE; + iobase2 &= 0xFFFFFFFE; + iobase3 &= 0xFFFFFFFE; + iobase4 &= 0xFFFFFFFE; + iobase5 &= 0xFFFFFFFE; + + /*check for mode */ + pci_read_config_byte (bdf, PCI_PMR, &pmr); + if (pmr > 1) { + printf ("combined mode not supported\n"); + return 1; + } + + pci_read_config_byte (bdf, PCI_PI, &pi); + if ((pi & 0x05) != 0x05) { + printf ("Sata is in Legacy mode\n"); + return 1; + } else { + printf ("sata is in Native mode\n"); + } + + /*MASTER CFG AND IO CFG */ + pci_read_config_word (bdf, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (bdf, PCI_COMMAND, cmd); + pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat); + + if (lat < 16) + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; + else if (lat > pcibios_max_latency) + lat = pcibios_max_latency; + pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat); + + return 0; +} + +int +sata_bus_probe (int port_no) +{ + int orig_mask, mask; + u16 pcs; + + mask = (PORT_PRESENT << port_no); + pci_read_config_word (bdf, PCI_PCS, &pcs); + orig_mask = (int) pcs & 0xff; + if ((orig_mask & mask) != mask) + return 0; + else + return 1; +} + +int +init_sata (void) +{ + u8 i, rv = 0; + + for (i = 0; i < CFG_SATA_MAXDEVICES; i++) { + sata_dev_desc[i].type = DEV_TYPE_UNKNOWN; + sata_dev_desc[i].if_type = IF_TYPE_IDE; + sata_dev_desc[i].dev = i; + sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + sata_dev_desc[i].blksz = 0; + sata_dev_desc[i].lba = 0; + sata_dev_desc[i].block_read = sata_read; + } + + rv = pci_sata_init (); + if (rv == 1) { + printf ("pci initialization failed\n"); + return 1; + } + + port[0].port_no = 0; + port[0].ioaddr.cmd_addr = iobase1; + port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = + iobase2 | ATA_PCI_CTL_OFS; + port[0].ioaddr.bmdma_addr = iobase5; + + port[1].port_no = 1; + port[1].ioaddr.cmd_addr = iobase3; + port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = + iobase4 | ATA_PCI_CTL_OFS; + port[1].ioaddr.bmdma_addr = iobase5 + 0x8; + + for (i = 0; i < CFG_SATA_MAXBUS; i++) + sata_port (&port[i].ioaddr); + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + if (!(sata_bus_probe (i))) { + port[i].port_state = 0; + printf ("SATA#%d port is not present \n", i); + } else { + printf ("SATA#%d port is present\n", i); + if (sata_bus_softreset (i)) { + port[i].port_state = 0; + } else { + port[i].port_state = 1; + } + } + } + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + u8 j, devno; + + if (port[i].port_state == 0) + continue; + for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) { + sata_identify (i, j); + set_Feature_cmd (i, j); + devno = i * CFG_SATA_DEVS_PER_BUS + j; + if ((sata_dev_desc[devno].lba > 0) && + (sata_dev_desc[devno].blksz > 0)) { + dev_print (&sata_dev_desc[devno]); + /* initialize partition type */ + init_part (&sata_dev_desc[devno]); + if (curr_dev < 0) + curr_dev = + i * CFG_SATA_DEVS_PER_BUS + j; + } + } + } + return 0; +} +#endif diff --git a/include/ata.h b/include/ata.h index 8584226eb0..d36bdf6cd1 100644 --- a/include/ata.h +++ b/include/ata.h @@ -83,6 +83,66 @@ #define ATA_DEVICE(x) ((x & 1)<<4) #define ATA_LBA 0xE0 +enum { + ATA_MAX_DEVICES = 1, /* per bus/port */ + ATA_MAX_PRD = 256, /* we could make these 256/256 */ + ATA_SECT_SIZE = 256, /*256 words per sector */ + + /* bits in ATA command block registers */ + ATA_HOB = (1 << 7), /* LBA48 selector */ + ATA_NIEN = (1 << 1), /* disable-irq flag */ + /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ + ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ + ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_ERR = (1 << 0), /* have an error */ + ATA_SRST = (1 << 2), /* software reset */ + ATA_ABORTED = (1 << 2), /* command aborted */ + /* ATA command block registers */ + ATA_REG_DATA = 0x00, + ATA_REG_ERR = 0x01, + ATA_REG_NSECT = 0x02, + ATA_REG_LBAL = 0x03, + ATA_REG_LBAM = 0x04, + ATA_REG_LBAH = 0x05, + ATA_REG_DEVICE = 0x06, + ATA_REG_STATUS = 0x07, + ATA_PCI_CTL_OFS = 0x02, + /* and their aliases */ + ATA_REG_FEATURE = ATA_REG_ERR, + ATA_REG_CMD = ATA_REG_STATUS, + ATA_REG_BYTEL = ATA_REG_LBAM, + ATA_REG_BYTEH = ATA_REG_LBAH, + ATA_REG_DEVSEL = ATA_REG_DEVICE, + ATA_REG_IRQ = ATA_REG_NSECT, + + /* SETFEATURES stuff */ + SETFEATURES_XFER = 0x03, + XFER_UDMA_7 = 0x47, + XFER_UDMA_6 = 0x46, + XFER_UDMA_5 = 0x45, + XFER_UDMA_4 = 0x44, + XFER_UDMA_3 = 0x43, + XFER_UDMA_2 = 0x42, + XFER_UDMA_1 = 0x41, + XFER_UDMA_0 = 0x40, + XFER_MW_DMA_2 = 0x22, + XFER_MW_DMA_1 = 0x21, + XFER_MW_DMA_0 = 0x20, + XFER_PIO_4 = 0x0C, + XFER_PIO_3 = 0x0B, + XFER_PIO_2 = 0x0A, + XFER_PIO_1 = 0x09, + XFER_PIO_0 = 0x08, + XFER_SW_DMA_2 = 0x12, + XFER_SW_DMA_1 = 0x11, + XFER_SW_DMA_0 = 0x10, + XFER_PIO_SLOW = 0x00 +}; /* * ATA Commands (only mandatory commands listed here) */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index d7d07a62fc..8b2ec077bd 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -181,6 +181,15 @@ #undef CONFIG_IDE_RESET /* reset for ide unsupported... */ #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ +/************************************************************ +*SATA/Native Stuff +************************************************************/ +#define CFG_SATA_SUPPORTED 1 +#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ +#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ +#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) +#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */ + /************************************************************ * ATAPI support (experimental) ************************************************************/ diff --git a/include/sata.h b/include/sata.h new file mode 100644 index 0000000000..c6fa2ab5bc --- /dev/null +++ b/include/sata.h @@ -0,0 +1,108 @@ + +#if (DEBUG_SATA) +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +struct sata_ioports { + unsigned long cmd_addr; + unsigned long data_addr; + unsigned long error_addr; + unsigned long feature_addr; + unsigned long nsect_addr; + unsigned long lbal_addr; + unsigned long lbam_addr; + unsigned long lbah_addr; + unsigned long device_addr; + unsigned long status_addr; + unsigned long command_addr; + unsigned long altstatus_addr; + unsigned long ctl_addr; + unsigned long bmdma_addr; + unsigned long scr_addr; +}; + +struct sata_port { + unsigned char port_no; /*primary-0, secondary=1 */ + struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char ctl_reg; + unsigned char last_ctl; + unsigned char port_state; /*1-port is present and + 0-port is not available */ + unsigned char dev_mask; +}; + +/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/ +#ifdef SATA_DECL /*SATA library specific declarations */ +#define ata_id_has_lba48(id) ((id)[83] & (1 << 10)) +#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) +#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) +#define ata_id_u32(id,n) \ + (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) +#define ata_id_u64(id,n) \ + (((u64) (id)[(n) + 3] << 48) | \ + ((u64) (id)[(n) + 2] << 32) | \ + ((u64) (id)[(n) + 1] << 16) | \ + ((u64) (id)[(n) + 0]) ) +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +static inline void +ata_dump_id (u16 * id) +{ + PRINTF ("49==0x%04x " + "53==0x%04x " + "63==0x%04x " + "64==0x%04x " + "75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]); + PRINTF ("80==0x%04x " + "81==0x%04x " + "82==0x%04x " + "83==0x%04x " + "84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]); + PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]); +} +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +int sata_bus_softreset (int num); +void sata_identify (int num, int dev); +void sata_port (struct sata_ioports *ioport); +void set_Feature_cmd (int num, int dev); +int sata_devchk (struct sata_ioports *ioaddr, int dev); +void dev_select (struct sata_ioports *ioaddr, int dev); +u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); +u8 sata_chk_status (struct sata_ioports *ioaddr); +ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +void msleep (int count); +#else +extern int sata_bus_softreset (int num); +extern void sata_identify (int num, int dev); +extern void sata_port (struct sata_ioports *ioport); +extern void set_Feature_cmd (int num, int dev); +extern ulong sata_read (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern ulong sata_write (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern void msleep (int count); +#endif + +/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/ + +#ifdef DRV_DECL /*Driver specific declaration */ +int init_sata (void); +#else +extern int init_sata (void); +#endif + +#ifdef DRV_DECL /*Defines Driver Specific variables */ +struct sata_port port[CFG_SATA_MAXBUS]; +block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +int curr_dev = -1; +#else +extern struct sata_port port[CFG_SATA_MAXBUS]; +extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +extern int curr_dev; +#endif -- cgit v1.2.1 From 3162eb836903c8b247fdc7470dd39bfa6996f495 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 May 2007 23:38:05 +0200 Subject: Minor coding style cleanup. --- common/cmd_sata.c | 52 +++++++++++++++++++++++++++------------------------- drivers/ata_piix.c | 46 +++++++++++++++++++++++----------------------- include/ata.h | 2 +- include/sata.h | 8 ++++---- 4 files changed, 55 insertions(+), 53 deletions(-) diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 1c71b6471d..2e601a7d80 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -1,29 +1,31 @@ /* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference to libata in kernel 2.4.32 - * -*/ - -/*File contains SATA read-write and other utility functions.*/ + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + * + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to libata in kernel 2.4.32 + * + */ + +/* + * File contains SATA read-write and other utility functions. + */ #include #include #include diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c index 7e611633be..42456d7be3 100644 --- a/drivers/ata_piix.c +++ b/drivers/ata_piix.c @@ -1,29 +1,29 @@ /* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference to ata_piix driver in kernel 2.4.32 -*/ + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to ata_piix driver in kernel 2.4.32 + */ /* -This file contains SATA controller and SATA drive initialization functions -*/ + * This file contains SATA controller and SATA drive initialization functions + */ #include #include diff --git a/include/ata.h b/include/ata.h index d36bdf6cd1..aa6e90d470 100644 --- a/include/ata.h +++ b/include/ata.h @@ -91,7 +91,7 @@ enum { /* bits in ATA command block registers */ ATA_HOB = (1 << 7), /* LBA48 selector */ ATA_NIEN = (1 << 1), /* disable-irq flag */ - /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + /*ATA_LBA = (1 << 6), */ /* LBA28 selector */ ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ diff --git a/include/sata.h b/include/sata.h index c6fa2ab5bc..a8713f817e 100644 --- a/include/sata.h +++ b/include/sata.h @@ -24,12 +24,12 @@ struct sata_ioports { }; struct sata_port { - unsigned char port_no; /*primary-0, secondary=1 */ - struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char port_no; /* primary=0, secondary=1 */ + struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /*1-port is present and - 0-port is not available */ + unsigned char port_state; /* 1-port is present and */ + 0-port is not available */ unsigned char dev_mask; }; -- cgit v1.2.1 From 255a3577c848706441daee0174543efe205a77f8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 16 May 2007 16:52:19 -0500 Subject: Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips --- board/cds/mpc8548cds/mpc8548cds.c | 10 +++++----- cpu/mpc83xx/cpu.c | 8 ++++---- cpu/mpc85xx/cpu.c | 2 +- cpu/mpc86xx/cpu.c | 8 ++++---- drivers/tsec.c | 18 ++++++++---------- include/configs/MPC8313ERDB.h | 8 ++++---- include/configs/MPC8349EMDS.h | 8 ++++---- include/configs/MPC8349ITX.h | 14 +++++++------- include/configs/MPC8540ADS.h | 8 ++++---- include/configs/MPC8540EVAL.h | 8 ++++---- include/configs/MPC8541CDS.h | 8 ++++---- include/configs/MPC8544DS.h | 8 ++++---- include/configs/MPC8548CDS.h | 16 ++++++++-------- include/configs/MPC8555CDS.h | 8 ++++---- include/configs/MPC8560ADS.h | 8 ++++---- include/configs/MPC8568MDS.h | 12 ++++++------ include/configs/MPC8641HPCN.h | 16 ++++++++-------- include/configs/PM854.h | 8 ++++---- include/configs/PM856.h | 8 ++++---- include/configs/TQM834x.h | 8 ++++---- include/configs/TQM85xx.h | 8 ++++---- include/configs/sbc8349.h | 8 ++++---- include/configs/stxgp3.h | 8 ++++---- include/configs/stxssa.h | 8 ++++---- net/eth.c | 39 ++++++++------------------------------- 25 files changed, 119 insertions(+), 144 deletions(-) diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 929ff2e662..b7236417e8 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -345,23 +345,23 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_read(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index e078f27a23..841fe82428 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -415,7 +415,7 @@ static const struct { "clock-frequency", fdt_set_busfreq }, -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 { "/" OF_SOC "/ethernet@24000, "mac-address", fdt_set_eth0 @@ -425,7 +425,7 @@ static const struct { fdt_set_eth0 }, #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 { "/" OF_SOC "/ethernet@25000, "mac-address", fdt_set_eth1 @@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); @@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enetaddr, 6); #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 7735a52ccf..1d791c9b9b 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_MPC85XX_TSEC1) +#if defined(CONFIG_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p) memcpy(p, bd->bi_enetaddr, 6); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index a33acfec4d..9456471e84 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_MPC86XX_TSEC1) +#if defined(CONFIG_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); @@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enetaddr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC2) +#if defined(CONFIG_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); @@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet1addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC3) +#if defined(CONFIG_TSEC3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet2addr, 6); @@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet2addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC4) +#if defined(CONFIG_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); diff --git a/drivers/tsec.c b/drivers/tsec.c index 790ba47c78..1298478704 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -65,33 +65,31 @@ struct tsec_info_struct { * FEC_PHYIDX */ static struct tsec_info_struct tsec_info[] = { -#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) -#if defined(CONFIG_MPC8544DS) +#if defined(CONFIG_TSEC1) +#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, #endif -#elif defined(CONFIG_MPC86XX_TSEC1) - {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, -#else {0, 0, 0}, #endif -#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) - {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, -#elif defined(CONFIG_MPC86XX_TSEC2) +#if defined(CONFIG_TSEC2) +#if defined(CONFIG_MPC8641HPCN) {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else + {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#endif {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, #else -#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) +#if defined(CONFIG_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4) +#if defined(CONFIG_TSEC4) {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, #else {0, 0, 0}, diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 697631345f..7e1005c1ae 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -303,11 +303,11 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 0460be9e56..20c6d5a365 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -432,10 +432,10 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 906339e9d8..834934d0b6 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ -#define CONFIG_MPC83XX_TSEC1 +#define CONFIG_TSEC1 -#ifdef CONFIG_MPC83XX_TSEC1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#ifdef CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_HAS_ETH1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 @@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5aeea58680..9176be388e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -366,10 +366,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 418a3a38e6..b568cb4df7 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -212,10 +212,10 @@ #elif defined(CONFIG_TSEC_ENET) #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index fb360d282c..e047e259a5 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4c3430897d..7cd62e95a9 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 680009d600..a0d291eef4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 -#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#undef CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c8b4e73f3..b7e703ca18 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 21e6637680..043397fc21 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -356,10 +356,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3f65644fdd..0ff0416138 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#undef CONFIG_MPC85XX_TSEC3 -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#undef CONFIG_TSEC3 +#undef CONFIG_TSEC4 #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bbe35053dd..43a9d6ff28 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -359,14 +359,14 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC86XX_TSEC1 1 -#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC86XX_TSEC2 1 -#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" -#define CONFIG_MPC86XX_TSEC3 1 -#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" -#define CONFIG_MPC86XX_TSEC4 1 -#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 4fb54402b1..8f130f5ccd 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -262,10 +262,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 87ab934873..0286b53e01 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -258,10 +258,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index ed0357791b..4a5f8b6757 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks; #define CONFIG_NET_MULTI #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f45f3a2f5a..b0b9dd3ab8 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -258,10 +258,10 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 65aac5cefd..e6e3866a07 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -401,10 +401,10 @@ #define CONFIG_NET_MULTI 1 #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_PHY_BCM5421S 1 #define TSEC1_PHY_ADDR 0x19 #define TSEC2_PHY_ADDR 0x1a diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 625cf20144..21065b9d05 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -230,10 +230,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 8624f4b74b..2a34185540 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -252,10 +252,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/net/eth.c b/net/eth.c index 0fc22115dc..ab56dcf6d5 100644 --- a/net/eth.c +++ b/net/eth.c @@ -173,28 +173,20 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_SK98) skge_initialize(bis); #endif -#if defined(CONFIG_MPC85XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME); -#elif defined(CONFIG_MPC83XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME); +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); #endif -#if defined(CONFIG_MPC85XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME); -#elif defined(CONFIG_MPC83XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME); +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); #endif #if defined(CONFIG_MPC85XX_FEC) tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); #else -# if defined(CONFIG_MPC85XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME); -# elif defined(CONFIG_MPC83XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME); +# if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); # endif -# if defined(CONFIG_MPC85XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME); -# elif defined(CONFIG_MPC83XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); +# if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); # endif #endif #if defined(CONFIG_UEC_ETH1) @@ -203,21 +195,6 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_UEC_ETH2) uec_initialize(1); #endif -#if defined(CONFIG_MPC86XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME); -#endif #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); -- cgit v1.2.1 From 822d55365bb557e084d0e33625a6dedcc866110b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 23 May 2007 14:09:46 -0500 Subject: Add LIST_86xx MAKEALL target for PowerPC builds. Signed-off-by: Jon Loeliger --- MAKEALL | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/MAKEALL b/MAKEALL index 04653a056d..6c8eb9c002 100755 --- a/MAKEALL +++ b/MAKEALL @@ -149,6 +149,14 @@ LIST_85xx=" \ TQM8560 \ " +######################################################################### +## MPC86xx Systems +######################################################################### + +LIST_86xx=" \ + MPC8641HPCN \ +" + ######################################################################### ## 74xx/7xx Systems ######################################################################### @@ -169,6 +177,7 @@ LIST_ppc="${LIST_5xx} ${LIST_5xxx} \ ${LIST_8220} ${LIST_824x} ${LIST_8260} \ ${LIST_83xx} \ ${LIST_85xx} \ + ${LIST_86xx} \ ${LIST_4xx} \ ${LIST_74xx} ${LIST_7xx}" @@ -355,7 +364,7 @@ do microblaze| \ mips|mips_el| \ nios|nios2| \ - ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \ + ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ x86|I486) for target in `eval echo '$LIST_'${arg}` do -- cgit v1.2.1 From 02032e8f14751a1a751b09240a4f1cf9f8a2077f Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 22 Jun 2007 14:58:04 +0200 Subject: [ppc] Fix build breakage for all non-4xx PowerPC variants. - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup --- cpu/74xx_7xx/start.S | 4 ++-- cpu/mpc5xx/start.S | 4 ++-- cpu/mpc5xxx/start.S | 4 ++-- cpu/mpc8220/start.S | 4 ++-- cpu/mpc824x/start.S | 4 ++-- cpu/mpc8260/start.S | 4 ++-- cpu/mpc83xx/start.S | 4 ++-- cpu/mpc85xx/start.S | 4 ++-- cpu/mpc86xx/start.S | 4 ++-- cpu/mpc8xx/start.S | 4 ++-- cpu/ppc4xx/start.S | 1 - include/74xx_7xx.h | 1 + include/mpc5xx.h | 1 + include/mpc5xxx.h | 1 + include/mpc8220.h | 1 + include/mpc824x.h | 2 ++ include/mpc8260.h | 2 +- include/mpc83xx.h | 1 + include/mpc85xx.h | 1 + include/mpc86xx.h | 2 +- include/mpc8xx.h | 2 +- include/ppc4xx.h | 3 ++- include/ppc_asm.tmpl | 2 +- 23 files changed, 34 insertions(+), 26 deletions(-) diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 11430388f5..b5834b91e3 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -125,7 +125,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -143,7 +143,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 087435e5be..95728373fb 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -210,7 +210,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -228,7 +228,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 3936b5551f..9b1bd48c73 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -208,7 +208,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -227,7 +227,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 52332023ec..b5145ca035 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -169,7 +169,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -188,7 +188,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 9ff052c3b0..784edc36a0 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -220,7 +220,7 @@ _start_of_vectors: /* Alignment exception. */ . = EXC_OFF_ALIGN Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -238,7 +238,7 @@ Alignment: /* Program check exception */ . = EXC_OFF_PROGRAM ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 2e93bbbb86..bc55b58ad2 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -279,7 +279,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -298,7 +298,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 6ee9ec96c9..496c8a5861 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -263,7 +263,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -282,7 +282,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 20c7ebc723..77c155c5bd 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -457,7 +457,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x0600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -475,7 +475,7 @@ Alignment: /* Program check exception */ . = 0x0700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 67c56db1a3..412745bdae 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -116,7 +116,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -134,7 +134,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 33a3f6c88e..eca4b50626 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -224,7 +224,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -242,7 +242,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a46197dde9..dfe813c3f4 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -60,7 +60,6 @@ * address and (s)dram will be positioned at address 0 */ #include -#include #include #include diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index ba73bae9e5..4a03cecb59 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -34,6 +34,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*---------------------------------------------------------------- * l2cr values diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 7508f6df20..e9b08a0dc7 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -36,6 +36,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * ISB bit in IMMR to set internal memory map diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 089aa1322b..a4581a3e6b 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -39,6 +39,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ #if defined(CONFIG_MGT5100) diff --git a/include/mpc8220.h b/include/mpc8220.h index ff7acc6d3a..d3b1457f9c 100644 --- a/include/mpc8220.h +++ b/include/mpc8220.h @@ -35,6 +35,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* Internal memory map */ /* MPC8220 Internal Register MMAP */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 30fc795382..4bd8863481 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -142,6 +142,8 @@ #define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ #define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ +#define _START_OFFSET EXC_OFF_SYS_RESET + #define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ diff --git a/include/mpc8260.h b/include/mpc8260.h index d9dd92d9a5..b61218ccc2 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -53,7 +53,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * BCR - Bus Configuration Register 4-25 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 60fc214b3e..cbf41c3a93 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -25,6 +25,7 @@ /* System reset offset (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* IMMRBAR - Internal Memory Register Base Address */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4d99b2a16..6fbd50457c 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -8,6 +8,7 @@ #define __MPC85xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET #if defined(CONFIG_E500) #include diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 673bfed16e..9fd349af98 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -8,7 +8,7 @@ #define __MPC86xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /* * platform register addresses diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 29117589be..11305987f8 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -35,7 +35,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register 11-9 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 8cead66ad1..ca241d2c13 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,7 +22,8 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define _START_OFFSET 0x2100 +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) #if defined(CONFIG_440) #include diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index ad027d61f4..9f4029f2af 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -274,7 +274,7 @@ label: \ #define CRIT_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ - EXCEPTION_PROLOG(csrr0, csrr1); \ + EXCEPTION_PROLOG(CSRR0, CSRR1); \ lwz r3,GOT(transfer_to_handler); \ mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ -- cgit v1.2.1 From 3a1f5c81b0b9557817a789bece839905581c2205 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 22 Jun 2007 16:58:40 +0200 Subject: ppc4xx: Fix problem with extended program_tlb() funtion The recently extended program_tlb() function had a problem when multiple TLB's had to be setup (for example with 512MB of SDRAM). The virtual address was not incremented. This patch fixes this issue and is tested on Katmai with 512MB SDRAM. Signed-off-by: Stefan Roese --- cpu/ppc4xx/tlb.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/cpu/ppc4xx/tlb.c b/cpu/ppc4xx/tlb.c index 6c916eff5b..049a785495 100644 --- a/cpu/ppc4xx/tlb.c +++ b/cpu/ppc4xx/tlb.c @@ -101,6 +101,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_256MB, tlb_i)) == 0) { mem_size -= TLB_256MB_SIZE; phys_addr += TLB_256MB_SIZE; + virt_addr += TLB_256MB_SIZE; } } else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_16MB_SIZE)) { @@ -109,6 +110,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_16MB, tlb_i)) == 0) { mem_size -= TLB_16MB_SIZE; phys_addr += TLB_16MB_SIZE; + virt_addr += TLB_16MB_SIZE; } } else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_1MB_SIZE)) { @@ -117,6 +119,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_1MB, tlb_i)) == 0) { mem_size -= TLB_1MB_SIZE; phys_addr += TLB_1MB_SIZE; + virt_addr += TLB_1MB_SIZE; } } else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_256KB_SIZE)) { @@ -125,6 +128,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_256KB, tlb_i)) == 0) { mem_size -= TLB_256KB_SIZE; phys_addr += TLB_256KB_SIZE; + virt_addr += TLB_256KB_SIZE; } } else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_64KB_SIZE)) { @@ -133,6 +137,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_64KB, tlb_i)) == 0) { mem_size -= TLB_64KB_SIZE; phys_addr += TLB_64KB_SIZE; + virt_addr += TLB_64KB_SIZE; } } else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_16KB_SIZE)) { @@ -141,6 +146,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_16KB, tlb_i)) == 0) { mem_size -= TLB_16KB_SIZE; phys_addr += TLB_16KB_SIZE; + virt_addr += TLB_16KB_SIZE; } } else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_4KB_SIZE)) { @@ -149,6 +155,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_4KB, tlb_i)) == 0) { mem_size -= TLB_4KB_SIZE; phys_addr += TLB_4KB_SIZE; + virt_addr += TLB_4KB_SIZE; } } else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) && (mem_size >= TLB_1KB_SIZE)) { @@ -157,6 +164,7 @@ static void program_tlb_addr(unsigned long phys_addr, TLB_WORD0_SIZE_1KB, tlb_i)) == 0) { mem_size -= TLB_1KB_SIZE; phys_addr += TLB_1KB_SIZE; + virt_addr += TLB_1KB_SIZE; } } else { printf("ERROR: no TLB size exists for the base address 0x%0X.\n", -- cgit v1.2.1 From a11e06965ec91270c51853407ff1261d3c740386 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 28 Mar 2007 19:06:19 +0400 Subject: Extend POST support for PPC440 Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin -- --- board/amcc/sequoia/sequoia.c | 10 ++ cpu/ppc4xx/cpu_init.c | 2 + include/configs/sequoia.h | 15 ++- include/post.h | 1 + include/ppc440.h | 50 +++++----- post/cpu/ppc4xx/Makefile | 28 ++++++ post/cpu/ppc4xx/fpu.c | 55 +++++++++++ post/cpu/ppc4xx/spr.c | 176 +++++++++++++++++++++++++++++++++++ post/cpu/ppc4xx/uart.c | 214 +++++++++++++++++++++++++++++++++++++++++++ post/cpu/ppc4xx/watchdog.c | 68 ++++++++++++++ post/lib_ppc/asm.S | 12 +++ post/lib_ppc/b.c | 8 +- post/post.c | 2 +- post/tests.c | 14 +++ 14 files changed, 625 insertions(+), 30 deletions(-) create mode 100644 post/cpu/ppc4xx/Makefile create mode 100644 post/cpu/ppc4xx/fpu.c create mode 100644 post/cpu/ppc4xx/spr.c create mode 100644 post/cpu/ppc4xx/uart.c create mode 100644 post/cpu/ppc4xx/watchdog.c diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index ba365aea31..b49179ba0d 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -586,3 +586,13 @@ int is_pci_host(struct pci_controller *hose) return (1); } #endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 66e8637260..bc1ae0e4e7 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -211,6 +211,8 @@ cpu_init_f (void) val = mfspr(tcr); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ +#elif defined(CONFIG_440EPX) + val |= 0xb0000000; /* generate system reset after 1.34 seconds */ #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f..ae1c129109 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -59,6 +59,7 @@ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -81,7 +82,7 @@ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -328,6 +329,18 @@ CFG_CMD_SDRAM | \ CMD_USB) +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_SPR) + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CONFIG_LOGBUFFER + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + #define CONFIG_SUPPORT_VFAT /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/post.h b/include/post.h index cdefbddb6f..8259e5d2ea 100644 --- a/include/post.h +++ b/include/post.h @@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_SYSMON 0x00000800 #define CFG_POST_DSP 0x00001000 #define CFG_POST_CODEC 0x00002000 +#define CFG_POST_FPU 0x00004000 #endif /* CONFIG_POST */ diff --git a/include/ppc440.h b/include/ppc440.h index 09f843041d..9ba47a53cf 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -282,6 +282,32 @@ #define sdr_sdstp3 0x4003 #endif /* CONFIG_440GX */ +#ifdef CONFIG_440 +/*----------------------------------------------------------------------------+ +| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). ++----------------------------------------------------------------------------*/ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SWOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF +#endif /* CONFIG_440 */ + #ifdef CONFIG_440SPE #undef sdr_sdstp2 #define sdr_sdstp2 0x0022 @@ -307,30 +333,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -/*----------------------------------------------------------------------------+ -| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). -+----------------------------------------------------------------------------*/ -#define CCR0_PRE 0x40000000 -#define CCR0_CRPE 0x08000000 -#define CCR0_DSTG 0x00200000 -#define CCR0_DAPUIB 0x00100000 -#define CCR0_DTB 0x00008000 -#define CCR0_GICBT 0x00004000 -#define CCR0_GDCBT 0x00002000 -#define CCR0_FLSTA 0x00000100 -#define CCR0_ICSLC_MASK 0x0000000C -#define CCR0_ICSLT_MASK 0x00000003 -#define CCR1_TCS_MASK 0x00000080 -#define CCR1_TCS_INTCLK 0x00000000 -#define CCR1_TCS_EXTCLK 0x00000080 -#define MMUCR_SEOA 0x01000000 -#define MMUCR_U1TE 0x00400000 -#define MMUCR_U2SWOAE 0x00200000 -#define MMUCR_DULXE 0x00800000 -#define MMUCR_IULXE 0x00400000 -#define MMUCR_STS 0x00100000 -#define MMUCR_STID_MASK 0x000000FF - #define SDR0_CFGADDR 0x00E #define SDR0_CFGDATA 0x00F diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile new file mode 100644 index 0000000000..8e8ab50577 --- /dev/null +++ b/post/cpu/ppc4xx/Makefile @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LIB = libpostppc4xx.a + +COBJS = fpu.o spr.o uart.o watchdog.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c new file mode 100644 index 0000000000..1935c011ba --- /dev/null +++ b/post/cpu/ppc4xx/fpu.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2007 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST +#if defined(CONFIG_440EP) || \ + defined(CONFIG_440EPX) + +#include +#include + + +int fpu_status(void) +{ + if (mfspr(ccr0) & CCR0_DAPUIB) + return 0; /* Disabled */ + else + return 1; /* Enabled */ +} + + +void fpu_disable(void) +{ + mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB); + mtmsr(mfmsr() & ~MSR_FP); +} + + +void fpu_enable(void) +{ + mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB); + mtmsr(mfmsr() | MSR_FP); +} +#endif +#endif diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c new file mode 100644 index 0000000000..f62526a171 --- /dev/null +++ b/post/cpu/ppc4xx/spr.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * SPR test + * + * The test checks the contents of Special Purpose Registers (SPR) listed + * in the spr_test_list array below. + * Each SPR value is read using mfspr instruction, some bits are masked + * according to the table and the resulting value is compared to the + * corresponding table value. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_SPR + +static struct +{ + int number; + char * name; + unsigned long mask; + unsigned long value; +} spr_test_list [] = { + /* Standard Special-Purpose Registers */ + + {0x001, "XER", 0x00000000, 0x00000000}, + {0x008, "LR", 0x00000000, 0x00000000}, + {0x009, "CTR", 0x00000000, 0x00000000}, + {0x016, "DEC", 0x00000000, 0x00000000}, + {0x01a, "SRR0", 0x00000000, 0x00000000}, + {0x01b, "SRR1", 0x00000000, 0x00000000}, + {0x110, "SPRG0", 0x00000000, 0x00000000}, + {0x111, "SPRG1", 0x00000000, 0x00000000}, + {0x112, "SPRG2", 0x00000000, 0x00000000}, + {0x113, "SPRG3", 0x00000000, 0x00000000}, + {0x11f, "PVR", 0x00000000, 0x00000000}, + + /* Additional Special-Purpose Registers */ + + {0x30, "PID", 0x00000000, 0x00000000}, + {0x3a, "CSRR0", 0x00000000, 0x00000000}, + {0x3b, "CSRR1", 0x00000000, 0x00000000}, + {0x3d, "DEAR", 0x00000000, 0x00000000}, + {0x3e, "ESR", 0x00000000, 0x00000000}, + {0x3f, "IVPR", 0xffff0000, 0x00000000}, + {0x100, "USPRG0", 0x00000000, 0x00000000}, + {0x104, "SPRG4", 0x00000000, 0x00000000}, + {0x105, "SPRG5", 0x00000000, 0x00000000}, + {0x106, "SPRG6", 0x00000000, 0x00000000}, + {0x107, "SPRG7", 0x00000000, 0x00000000}, + {0x10c, "TBL", 0x00000000, 0x00000000}, + {0x10d, "TBU", 0x00000000, 0x00000000}, + {0x11e, "PIR", 0x0000000f, 0x00000000}, + {0x130, "DBSR", 0x00000000, 0x00000000}, + {0x134, "DBCR0", 0x00000000, 0x00000000}, + {0x135, "DBCR1", 0x00000000, 0x00000000}, + {0x136, "DBCR2", 0x00000000, 0x00000000}, + {0x138, "IAC1", 0x00000000, 0x00000000}, + {0x139, "IAC2", 0x00000000, 0x00000000}, + {0x13a, "IAC3", 0x00000000, 0x00000000}, + {0x13b, "IAC4", 0x00000000, 0x00000000}, + {0x13c, "DAC1", 0x00000000, 0x00000000}, + {0x13d, "DAC2", 0x00000000, 0x00000000}, + {0x13e, "DVC1", 0x00000000, 0x00000000}, + {0x13f, "DVC2", 0x00000000, 0x00000000}, + {0x150, "TSR", 0x00000000, 0x00000000}, + {0x154, "TCR", 0x00000000, 0x00000000}, + {0x190, "IVOR0", 0x00000000, 0x00000000}, + {0x191, "IVOR1", 0x00000000, 0x00000000}, + {0x192, "IVOR2", 0x00000000, 0x00000000}, + {0x193, "IVOR3", 0x00000000, 0x00000000}, + {0x194, "IVOR4", 0x00000000, 0x00000000}, + {0x195, "IVOR5", 0x00000000, 0x00000000}, + {0x196, "IVOR6", 0x00000000, 0x00000000}, + {0x197, "IVOR7", 0x00000000, 0x00000000}, + {0x198, "IVOR8", 0x00000000, 0x00000000}, + {0x199, "IVOR9", 0x00000000, 0x00000000}, + {0x19a, "IVOR10", 0x00000000, 0x00000000}, + {0x19b, "IVOR11", 0x00000000, 0x00000000}, + {0x19c, "IVOR12", 0x00000000, 0x00000000}, + {0x19d, "IVOR13", 0x00000000, 0x00000000}, + {0x19e, "IVOR14", 0x00000000, 0x00000000}, + {0x19f, "IVOR15", 0x00000000, 0x00000000}, + {0x23a, "MCSRR0", 0x00000000, 0x00000000}, + {0x23b, "MCSRR1", 0x00000000, 0x00000000}, + {0x23c, "MCSR", 0x00000000, 0x00000000}, + {0x370, "INV0", 0x00000000, 0x00000000}, + {0x371, "INV1", 0x00000000, 0x00000000}, + {0x372, "INV2", 0x00000000, 0x00000000}, + {0x373, "INV3", 0x00000000, 0x00000000}, + {0x374, "ITV0", 0x00000000, 0x00000000}, + {0x375, "ITV1", 0x00000000, 0x00000000}, + {0x376, "ITV2", 0x00000000, 0x00000000}, + {0x377, "ITV3", 0x00000000, 0x00000000}, + {0x378, "CCR1", 0x00000000, 0x00000000}, + {0x390, "DNV0", 0x00000000, 0x00000000}, + {0x391, "DNV1", 0x00000000, 0x00000000}, + {0x392, "DNV2", 0x00000000, 0x00000000}, + {0x393, "DNV3", 0x00000000, 0x00000000}, + {0x394, "DTV0", 0x00000000, 0x00000000}, + {0x395, "DTV1", 0x00000000, 0x00000000}, + {0x396, "DTV2", 0x00000000, 0x00000000}, + {0x397, "DTV3", 0x00000000, 0x00000000}, + {0x398, "DVLIM", 0x00000000, 0x00000000}, + {0x399, "IVLIM", 0x00000000, 0x00000000}, + {0x39b, "RSTCFG", 0x00000000, 0x00000000}, + {0x39c, "DCDBTRL", 0x00000000, 0x00000000}, + {0x39d, "DCDBTRH", 0x00000000, 0x00000000}, + {0x39e, "ICDBTRL", 0x00000000, 0x00000000}, + {0x39f, "ICDBTRH", 0x00000000, 0x00000000}, + {0x3b2, "MMUCR", 0x00000000, 0x00000000}, + {0x3b3, "CCR0", 0x00000000, 0x00000000}, + {0x3d3, "ICDBDR", 0x00000000, 0x00000000}, + {0x3f3, "DBDR", 0x00000000, 0x00000000}, +}; + +static int spr_test_list_size = + sizeof (spr_test_list) / sizeof (spr_test_list[0]); + +int spr_post_test (int flags) +{ + int ret = 0; + int i; + + unsigned long code[] = { + 0x7c6002a6, /* mfspr r3,SPR */ + 0x4e800020 /* blr */ + }; + unsigned long (*get_spr) (void) = (void *) code; + + for (i = 0; i < spr_test_list_size; i++) { + int num = spr_test_list[i].number; + + /* mfspr r3,num */ + code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); + + asm volatile ("isync"); + + if ((get_spr () & spr_test_list[i].mask) != + (spr_test_list[i].value & spr_test_list[i].mask)) { + post_log ("The value of %s special register " + "is incorrect: 0x%08X\n", + spr_test_list[i].name, get_spr ()); + ret = -1; + } + } + + return ret; +} +#endif /* CONFIG_POST & CFG_POST_SPR */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c new file mode 100644 index 0000000000..f220dba17a --- /dev/null +++ b/post/cpu/ppc4xx/uart.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * UART test + * + * The controllers are configured to loopback mode and several + * characters are transmitted. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_UART + +#include +#include + +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500 +#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600 + +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#define UART2_SDR sdr_uart2 +#define UART3_SDR sdr_uart3 +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* + Line Status Register. +*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +DECLARE_GLOBAL_DATA_PTR; + +static int uart_post_init (unsigned long dev_base) +{ + unsigned long reg; + unsigned long udiv; + unsigned short bdiv; + volatile char val; +#ifdef CFG_EXT_SERIAL_CLOCK + unsigned long tmp; +#endif + int i; + + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) + break; + udelay (100); + } + MFREG(UART0_SDR, reg); + reg &= ~CR0_MASK; + +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + /* For 440, the cpu clock is on divider chain A, UART on divider + * chain B ... so cpu clock is irrelevant. Get the "optimized" + * values that are subject to the 1/2 opb clock constraint + */ + serial_divs (gd->baudrate, &udiv, &bdiv); +#endif + + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); +#endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); +#endif +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif + + out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */ + val = in8(dev_base + UART_LSR); /* clear line status */ + val = in8(dev_base + UART_RBR); /* read receive buffer */ + out8(dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */ + + return 0; +} + +static void uart_post_putc (unsigned long dev_base, char c) +{ + int i; + + out8 (dev_base + UART_THR, c); /* put character out */ + + /* Wait for transfer completion */ + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) + break; + udelay (100); + } +} + +static int uart_post_getc (unsigned long dev_base) +{ + int i; + + /* Wait for character available */ + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1) + break; + udelay (100); + } + return 0xff & in8 (dev_base + UART_RBR); +} + +static int test_ctlr (unsigned long dev_base, int index) +{ + int res = -1; + char test_str[] = "*** UART Test String ***\r\n"; + int i; + + uart_post_init (dev_base); + + for (i = 0; i < sizeof (test_str) - 1; i++) { + uart_post_putc (dev_base, test_str[i]); + if (uart_post_getc (dev_base) != test_str[i]) + goto done; + } + res = 0; +done: + if (res) + post_log ("uart%d test failed\n", index); + + return res; +} + +int uart_post_test (int flags) +{ + int i, res = 0; + static unsigned long base[] = { + UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE + }; + + for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) { + if (test_ctlr (base[i], i)) + res = -1; + } + serial_reinit_all (); + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_UART */ + +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c new file mode 100644 index 0000000000..3c76cfd348 --- /dev/null +++ b/post/cpu/ppc4xx/watchdog.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Watchdog test + * + * The test verifies the watchdog timer operation. + * On the first iteration, the test routine disables interrupts and + * makes a 10-second delay. If the system does not reboot during this delay, + * the watchdog timer is not operational and the test fails. If the system + * reboots, on the second iteration the test routine reports a success. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_WATCHDOG + +int watchdog_post_test (int flags) +{ + if (flags & POST_REBOOT) { + /* Test passed */ + + return 0; + } else { + /* 10-second delay */ + int ints = disable_interrupts (); + ulong base = post_time_ms (0); + + while (post_time_ms (base) < 10000) + ; + if (ints) + enable_interrupts (); + + /* + * If we have reached this point, the watchdog timer + * does not work + */ + return -1; + } +} + +#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S index a0815a43a7..5e72b3418f 100644 --- a/post/lib_ppc/asm.S +++ b/post/lib_ppc/asm.S @@ -34,6 +34,7 @@ /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 cpu_post_exec_02: + isync mflr r0 stwu r0, -4(r1) @@ -56,6 +57,7 @@ cpu_post_exec_02: /* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ .global cpu_post_exec_04 cpu_post_exec_04: + isync mflr r0 stwu r0, -4(r1) @@ -80,6 +82,7 @@ cpu_post_exec_04: /* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ .global cpu_post_exec_12 cpu_post_exec_12: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -100,6 +103,7 @@ cpu_post_exec_12: /* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ .global cpu_post_exec_11 cpu_post_exec_11: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -119,6 +123,7 @@ cpu_post_exec_11: /* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ .global cpu_post_exec_21 cpu_post_exec_21: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -148,6 +153,7 @@ cpu_post_exec_21: ulong op2); */ .global cpu_post_exec_22 cpu_post_exec_22: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -177,6 +183,7 @@ cpu_post_exec_22: /* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ .global cpu_post_exec_12w cpu_post_exec_12w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -198,6 +205,7 @@ cpu_post_exec_12w: /* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ .global cpu_post_exec_11w cpu_post_exec_11w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -218,6 +226,7 @@ cpu_post_exec_11w: /* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ .global cpu_post_exec_22w cpu_post_exec_22w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -241,6 +250,7 @@ cpu_post_exec_22w: /* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ .global cpu_post_exec_21w cpu_post_exec_21w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -263,6 +273,7 @@ cpu_post_exec_21w: /* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ .global cpu_post_exec_21x cpu_post_exec_21x: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -286,6 +297,7 @@ cpu_post_exec_21x: ulong cr); */ .global cpu_post_exec_31 cpu_post_exec_31: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c index b4b17c8ff0..6e276c48d5 100644 --- a/post/lib_ppc/b.c +++ b/post/lib_ppc/b.c @@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, ulong cr); static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, - int pjump, int dec, int link, ulong pctr, ulong cr) + int pjump, int decr, int link, ulong pctr, ulong cr) { int ret = 0; ulong lr = 0; @@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, ret = pjump == jump ? 0 : -1; if (ret == 0) { - if (dec) + if (decr) ret = pctr == ctr + 1 ? 0 : -1; else ret = pctr == ctr ? 0 : -1; @@ -163,7 +163,7 @@ int cpu_post_test_b (void) { for (ctr = 1; ctr <= 2 && ret == 0; ctr++) { - int dec = cd < 2; + int decr = cd < 2; int cr = cond ? 0x80000000 : 0x00000000; int jumpc = cc >= 2 || (cc == 0 && !cond) || @@ -174,7 +174,7 @@ int cpu_post_test_b (void) int jump = jumpc && jumpd; ret = cpu_post_test_bc (link ? OP_BCL : OP_BC, - (cc << 3) + (cd << 1), 0, jump, dec, link, + (cc << 3) + (cd << 1), 0, jump, decr, link, ctr, cr); if (ret != 0) diff --git a/post/post.c b/post/post.c index ac41990860..28435cc4af 100644 --- a/post/post.c +++ b/post/post.c @@ -428,7 +428,7 @@ void post_reloc (void) unsigned long post_time_ms (unsigned long base) { #ifdef CONFIG_PPC - return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base; + return (unsigned long)(get_ticks () / (get_tbclk () / CFG_HZ)) - base; #else #warning "Not implemented yet" return 0; /* Not implemented yet */ diff --git a/post/tests.c b/post/tests.c index 3bccd1a8ed..f3604b2493 100644 --- a/post/tests.c +++ b/post/tests.c @@ -37,6 +37,7 @@ extern int i2c_post_test (int flags); extern int rtc_post_test (int flags); extern int memory_post_test (int flags); extern int cpu_post_test (int flags); +extern int fpu_post_test (int flags); extern int uart_post_test (int flags); extern int ether_post_test (int flags); extern int spi_post_test (int flags); @@ -126,6 +127,19 @@ struct post_test post_list[] = CFG_POST_CPU }, #endif +#if CONFIG_POST & CFG_POST_FPU + { + "FPU test", + "fpu", + "This test verifies the arithmetic logic unit of" + " FPU.", + POST_RAM | POST_ALWAYS, + &fpu_post_test, + NULL, + NULL, + CFG_POST_FPU + }, +#endif #if CONFIG_POST & CFG_POST_UART { "UART test", -- cgit v1.2.1 From 2dc64451b4c08ffd619372abfdc2506a2e2363b9 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 18 Apr 2007 14:55:19 +0400 Subject: Adapt log buffer code to support Linux 2.6 A new environment variable, "logversion", selects the log buffer behaviour. If it is not set or set to a value other than 2, then the old, Linux 2.4.4, behaviour is selected. Signed-off-by: Igor Lisitsin -- --- common/cmd_log.c | 116 +++++++++++++++++++++++++++++++++--------------------- include/logbuff.h | 26 +++++++++++- 2 files changed, 96 insertions(+), 46 deletions(-) diff --git a/common/cmd_log.c b/common/cmd_log.c index 042a403026..5bf811e755 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2007 * Detlev Zundel, DENX Software Engineering, dzu@denx.de. * * Code used from linux/kernel/printk.c @@ -60,45 +60,40 @@ static char buf[1024]; /* This combination will not print messages with the default loglevel */ static unsigned console_loglevel = 3; static unsigned default_message_loglevel = 4; -static unsigned char *log_buf = NULL; -static unsigned long *ext_log_size; -static unsigned long *ext_log_start; -static unsigned long *ext_logged_chars; -#define log_size (*ext_log_size) -#define log_start (*ext_log_start) -#define logged_chars (*ext_logged_chars) +static unsigned log_version = 1; +static logbuff_t *log; -/* Forced by code, eh! */ -#define LOGBUFF_MAGIC 0xc0de4ced - -/* The mapping used here has to be the same as in setup_ext_logbuff () - in linux/kernel/printk */ void logbuff_init_ptrs (void) { - unsigned long *ext_tag; - unsigned long post_word; + unsigned long tag, post_word; char *s; - log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN); - ext_tag = (unsigned long *)(log_buf)-4; - ext_log_start = (unsigned long *)(log_buf)-3; - ext_log_size = (unsigned long *)(log_buf)-2; - ext_logged_chars = (unsigned long *)(log_buf)-1; + log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1; + + /* Set up log version */ + if ((s = getenv ("logversion")) != NULL) + log_version = (int)simple_strtoul (s, NULL, 10); + + if (log_version == 2) + tag = log->v2.tag; + else + tag = log->v1.tag; post_word = post_word_load(); #ifdef CONFIG_POST /* The post routines have setup the word so we can simply test it */ - if (post_word_load () & POST_COLDBOOT) { - logged_chars = log_size = log_start = 0; - *ext_tag = LOGBUFF_MAGIC; + if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) { + logbuff_reset (); } #else /* No post routines, so we do our own checking */ - if (post_word != LOGBUFF_MAGIC) { - logged_chars = log_size = log_start = 0; + if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) { + logbuff_reset (); post_word_store (LOGBUFF_MAGIC); - *ext_tag = LOGBUFF_MAGIC; } #endif + if (log_version == 2 && (long)log->v2.start > (long)log->v2.con) + log->v2.start = log->v2.con; + /* Initialize default loglevel if present */ if ((s = getenv ("loglevel")) != NULL) console_loglevel = (int)simple_strtoul (s, NULL, 10); @@ -106,6 +101,15 @@ void logbuff_init_ptrs (void) gd->post_log_word |= LOGBUFF_INITIALIZED; } +void logbuff_reset (void) +{ + memset (log, 0, sizeof (logbuff_t)); + if (log_version == 2) + log->v2.tag = LOGBUFF_MAGIC; + else + log->v1.tag = LOGBUFF_MAGIC; +} + int drv_logbuff_init (void) { device_t logdev; @@ -162,7 +166,7 @@ void logbuff_log(char *msg) int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *s; - unsigned long i; + unsigned long i, start, size; if (strcmp(argv[1],"append") == 0) { /* Log concatenation of all arguments separated by spaces */ @@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: if (strcmp(argv[1],"show") == 0) { - for (i=0; i < (log_size&LOGBUFF_MASK); i++) { - s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK); + if (log_version == 2) { + start = log->v2.start; + size = log->v2.end - log->v2.start; + } + else { + start = log->v1.start; + size = log->v1.size; + } + for (i=0; i < (size&LOGBUFF_MASK); i++) { + s = (char *)log->buf+((start+i)&LOGBUFF_MASK); putc (*s); } return 0; } else if (strcmp(argv[1],"reset") == 0) { - log_start = 0; - log_size = 0; - logged_chars = 0; + logbuff_reset (); return 0; } else if (strcmp(argv[1],"info") == 0) { - printf ("Logbuffer at %08lx\n", (unsigned long)log_buf); - printf ("log_start = %08lx\n", log_start); - printf ("log_size = %08lx\n", log_size); - printf ("logged_chars = %08lx\n", logged_chars); + printf ("Logbuffer at %08lx\n", (unsigned long)log->buf); + if (log_version == 2) { + printf ("log_start = %08lx\n", log->v2.start); + printf ("log_end = %08lx\n", log->v2.end); + printf ("logged_chars = %08lx\n", log->v2.chars); + } + else { + printf ("log_start = %08lx\n", log->v1.start); + printf ("log_size = %08lx\n", log->v1.size); + printf ("logged_chars = %08lx\n", log->v1.chars); + } return 0; } printf ("Usage:\n%s\n", cmdtp->usage); @@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } } -#if defined(CONFIG_LOGBUFFER) + U_BOOT_CMD( log, 255, 1, do_log, "log - manipulate logbuffer\n", @@ -211,7 +228,7 @@ U_BOOT_CMD( "log show - show contents\n" "log append - append to the logbuffer\n" ); -#endif /* CONFIG_LOGBUFFER */ + static int logbuff_printk(const char *line) { int i; @@ -241,13 +258,22 @@ static int logbuff_printk(const char *line) } line_feed = 0; for (; p < buf_end; p++) { - log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p; - if (log_size < LOGBUFF_LEN) - log_size++; - else - log_start++; - - logged_chars++; + if (log_version == 2) { + log->buf[log->v2.end & LOGBUFF_MASK] = *p; + log->v2.end++; + if (log->v2.end - log->v2.start > LOGBUFF_LEN) + log->v2.start++; + log->v2.chars++; + } + else { + log->buf[(log->v1.start + log->v1.size) & + LOGBUFF_MASK] = *p; + if (log->v1.size < LOGBUFF_LEN) + log->v1.size++; + else + log->v1.start++; + log->v1.chars++; + } if (*p == '\n') { line_feed = 1; break; diff --git a/include/logbuff.h b/include/logbuff.h index 3acfc18a78..d415729053 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2007 * Detlev Zundel, dzu@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ #ifdef CONFIG_LOGBUFFER +#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */ #define LOGBUFF_LEN (16384) /* Must be 16k right now */ #define LOGBUFF_MASK (LOGBUFF_LEN-1) #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ @@ -32,6 +33,29 @@ #define LOGBUFF_INITIALIZED (1<<31) +/* The mapping used here has to be the same as in setup_ext_logbuff () + in linux/kernel/printk */ + +typedef struct { + union { + struct { + unsigned long tag; + unsigned long start; + unsigned long con; + unsigned long end; + unsigned long chars; + } v2; + struct { + unsigned long dummy; + unsigned long tag; + unsigned long start; + unsigned long size; + unsigned long chars; + } v1; + }; + unsigned char buf[0]; +} logbuff_t; + int drv_logbuff_init (void); void logbuff_init_ptrs (void); void logbuff_log(char *msg); -- cgit v1.2.1 From 1636d1c8529c006d106287cfbc20cd0a246fe1cb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 22 Jun 2007 23:59:00 +0200 Subject: Coding stylke cleanup; rebuild CHANGELOG --- CHANGELOG | 39 +++++++++++++++++++++++++++++++++ board/amcc/acadia/acadia.c | 14 ++++++------ board/bf537-stamp/ether_bf537.c | 2 +- board/bf537-stamp/flash-defines.h | 6 ++--- board/bf537-stamp/stm_m25p64.c | 2 +- board/bf537-stamp/u-boot.lds.S | 12 +++++----- board/smdk2400/lowlevel_init.S | 2 +- common/cmd_log.c | 4 ++-- common/main.c | 2 +- cpu/mpc5xx/start.S | 2 +- cpu/mpc8260/start.S | 4 ++-- cpu/ppc4xx/44x_spd_ddr.c | 4 ++-- cpu/ppc4xx/44x_spd_ddr2.c | 4 ++-- cpu/ppc4xx/cpu_init.c | 2 +- include/asm-ppc/processor.h | 46 +++++++++++++++++++-------------------- include/configs/TQM5200.h | 4 ++-- include/configs/alpr.h | 4 ++-- include/configs/bamboo.h | 14 ++++++------ include/configs/ebony.h | 2 +- include/configs/lwmon5.h | 4 ++-- include/configs/ocotea.h | 2 +- include/configs/p3p440.h | 2 +- include/configs/pcs440ep.h | 2 +- include/configs/sequoia.h | 2 +- include/configs/taishan.h | 4 ++-- include/configs/yosemite.h | 2 +- include/mpc5xx.h | 42 +++++++++++++++++------------------ include/mpc824x.h | 6 ++--- include/mpc8260.h | 16 +++++++------- include/mpc83xx.h | 10 ++++----- include/mpc8xx.h | 12 +++++----- include/ppc405.h | 14 ++++++------ include/ppc440.h | 8 +++---- 33 files changed, 167 insertions(+), 128 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 08f625af01..e3c21f9bd8 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,42 @@ +commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9 +Author: Igor Lisitsin +Date: Wed Apr 18 14:55:19 2007 +0400 + + Adapt log buffer code to support Linux 2.6 + + A new environment variable, "logversion", selects the log buffer + behaviour. If it is not set or set to a value other than 2, then the + old, Linux 2.4.4, behaviour is selected. + + Signed-off-by: Igor Lisitsin + -- + +commit a11e06965ec91270c51853407ff1261d3c740386 +Author: Igor Lisitsin +Date: Wed Mar 28 19:06:19 2007 +0400 + + Extend POST support for PPC440 + + Added memory, CPU, UART, I2C and SPR POST tests for PPC440. + + Signed-off-by: Igor Lisitsin + -- + +commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f +Author: Rafal Jaworowski +Date: Fri Jun 22 14:58:04 2007 +0200 + + [ppc] Fix build breakage for all non-4xx PowerPC variants. + + - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros + - minor 4xx cleanup + +commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b +Author: Wolfgang Denk +Date: Wed Jun 20 18:14:24 2007 +0200 + + Coding style cleanup. Refresh CHANGELOG. + commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024 Author: Stefan Roese Date: Tue Jun 19 17:22:44 2007 +0200 diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 0f54025fb2..8b82ea40ed 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -31,13 +31,13 @@ static void acadia_gpio_init(void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ /* * Ultra (405EZ) was nice enough to add another GPIO controller diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c index f00837aad2..807b9e839b 100644 --- a/board/bf537-stamp/ether_bf537.c +++ b/board/bf537-stamp/ether_bf537.c @@ -48,7 +48,7 @@ #define TXBUF_BASE_ADDR 0xFF800000 #define TX_BUF_CNT 1 -#define TOUT_LOOP 1000000 +#define TOUT_LOOP 1000000 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h index acc1e8638b..1fa7a10bda 100644 --- a/board/bf537-stamp/flash-defines.h +++ b/board/bf537-stamp/flash-defines.h @@ -44,9 +44,9 @@ #define ERASE_SECT 6 #define READ 7 #define GET_SECTNUM 8 -#define FLASH_START_L 0x0000 -#define FLASH_START_H 0x2000 -#define FLASH_MAN_ST 2 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_MAN_ST 2 #define RESET_VAL 0xF0 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c index 7077e85f41..d9c08ee8e6 100644 --- a/board/bf537-stamp/stm_m25p64.c +++ b/board/bf537-stamp/stm_m25p64.c @@ -9,7 +9,7 @@ /* Application definitions */ -#define NUM_SECTORS 128 /* number of sectors */ +#define NUM_SECTORS 128 /* number of sectors */ #define SECTOR_SIZE 0x10000 #define NOP_NUM 1000 diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 3fb2d0cc60..8632097b61 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); __DYNAMIC = 0; */ MEMORY { - ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024) + ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024) l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000 l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000 } @@ -47,11 +47,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -68,7 +68,7 @@ SECTIONS .text : { /* WARNING - the following is hand-optimized to fit within */ - /* the sector before the environment sector. If it throws */ + /* the sector before the environment sector. If it throws */ /* an error during compilation remove an object here to get */ /* it linked after the configuration sector. */ diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S index a5de806af5..a7959f391d 100644 --- a/board/smdk2400/lowlevel_init.S +++ b/board/smdk2400/lowlevel_init.S @@ -117,7 +117,7 @@ #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ #define Trp 0x0 /* 2 clk */ #define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ +#define Tchr 0x2 /* 3 clk */ #define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ diff --git a/common/cmd_log.c b/common/cmd_log.c index 5bf811e755..fba8bd8bf5 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -83,13 +83,13 @@ void logbuff_init_ptrs (void) /* The post routines have setup the word so we can simply test it */ if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) { logbuff_reset (); - } + } #else /* No post routines, so we do our own checking */ if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) { logbuff_reset (); post_word_store (LOGBUFF_MAGIC); - } + } #endif if (log_version == 2 && (long)log->v2.start > (long)log->v2.con) log->v2.start = log->v2.con; diff --git a/common/main.c b/common/main.c index 553ac357dc..d8123a7ce8 100644 --- a/common/main.c +++ b/common/main.c @@ -962,7 +962,7 @@ int readline (const char *const prompt) n = 0; continue; - case 0x17: /* ^W - erase word */ + case 0x17: /* ^W - erase word */ p=delete_char(console_buffer, p, &col, &n, plen); while ((n > 0) && (*p != ' ')) { p=delete_char(console_buffer, p, &col, &n, plen); diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 95728373fb..0637003ce2 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -155,7 +155,7 @@ in_flash: /* Initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ + lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ lis r2, CFG_INIT_SP_ADDR@h ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ /* Note: R0 is still 0 here */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index bc55b58ad2..7f5dc819cd 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -676,13 +676,13 @@ init_debug: bdnz 1b /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ + /* */ /* The address to load is stored in the first word of dual port */ /* ram and should be preserved while the power is on, so you */ /* can plug addresses into that location then reset the cpu and */ /* this code will load that address into the IABR after the */ /* reset. */ - /* */ + /* */ /* When the program counter matches the contents of the IABR, */ /* an exception is generated (before the instruction at that */ /* location completes). The vector for this exception is 0x1300 */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index fe7bbabd59..e24cd81b71 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, */ cr |= SDRAM_BXCR_SDBE; - for (i = 0; i < num_banks; i++) { + for (i = 0; i < num_banks; i++) { bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = (4 << 20) * bank_size_id; bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", dimm_num, i, ctrl_bank_num[dimm_num]+i, bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); - } + } } } diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 874cec07ed..b5c0f53d27 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -58,8 +58,8 @@ #define SDRAM_DDR2 2 #define SDRAM_NONE 0 -#define MAXDIMMS 2 -#define MAXRANKS 4 +#define MAXDIMMS 2 +#define MAXRANKS 4 #define MAXBXCF 4 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bc1ae0e4e7..351da36e85 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -153,7 +153,7 @@ cpu_init_f (void) */ asm volatile(" bl 0f" ::: "lr"); asm volatile("0: mflr 3" ::: "r3"); - asm volatile(" addi 4, 0, 14" ::: "r4"); + asm volatile(" addi 4, 0, 14" ::: "r4"); asm volatile(" mtctr 4" ::: "ctr"); asm volatile("1: icbt 0, 3"); asm volatile(" addi 3, 3, 32" ::: "r3"); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 29e6101a15..9780fe15c0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -35,18 +35,18 @@ #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ #define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IR (1<<5) /* Instruction Relocate */ #define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DR (1<<4) /* Data Relocate */ #define MSR_DS (1<<4) /* Book E Data space */ #define MSR_PE (1<<3) /* Protection Enable */ #define MSR_PX (1<<2) /* Protection Exclusive Mode */ #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ #define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI @@ -123,9 +123,9 @@ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ @@ -266,7 +266,7 @@ #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ @@ -495,17 +495,17 @@ #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ #define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ +#define EAR SPRN_EAR /* External Address Register */ #define ESR SPRN_ESR /* Exception Syndrome Register */ #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ @@ -522,13 +522,13 @@ #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) @@ -540,7 +540,7 @@ #define SVR SPRN_SVR /* System-On-Chip Version Register */ #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ #define SPR1 SPRN_SPRG1 #define SPR2 SPRN_SPRG2 @@ -611,7 +611,7 @@ #define IVOR35 SPRN_IVOR35 #define MCSRR0 SPRN_MCSRR0 #define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 +#define L1CSR0 SPRN_L1CSR0 #define L1CSR1 SPRN_L1CSR1 #define MCSR SPRN_MCSR #define MMUCSR0 SPRN_MMUCSR0 @@ -620,7 +620,7 @@ #define PID1 SPRN_PID1 #define PID2 SPRN_PID2 #define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 +#define MAS1 SPRN_MAS1 #define MAS2 SPRN_MAS2 #define MAS3 SPRN_MAS3 #define MAS4 SPRN_MAS4 @@ -632,7 +632,7 @@ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ #define BESR_DMES 0x40000000 /* DMA Error Status */ #define BESR_RWS 0x20000000 /* Read/Write Status */ #define BESR_ETMASK 0x1C000000 /* Error Type */ @@ -689,8 +689,8 @@ #define IOCR_E3LP 0x01000000 #define IOCR_E4TE 0x00800000 #define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 #define IOCR_EDO 0x00008000 #define IOCR_2XC 0x00004000 #define IOCR_ATC 0x00002000 @@ -815,7 +815,7 @@ #define PVR_823 PVR_821 #define PVR_850 PVR_821 #define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 +#define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 9da1d884b1..aa3627b4d7 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -44,7 +44,7 @@ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ @@ -238,7 +238,7 @@ "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" #else -#define CUSTOM_ENV_SETTINGS \ +#define CUSTOM_ENV_SETTINGS \ "bootfile=cam5200/uImage\0" \ "u-boot=cam5200/u-boot.bin\0" \ "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824d..3e571db0e1 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -95,7 +95,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -257,7 +257,7 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8e..cd5844363f 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -74,9 +74,9 @@ * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -115,8 +115,8 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -126,11 +126,11 @@ #define CFG_FLASH_ADDR1 0x2aa #define CFG_FLASH_WORD_SIZE unsigned char -#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ -#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9ae..09efe1d400 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -122,7 +122,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267..ab42b59626 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -117,7 +117,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -360,7 +360,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fdd..931fb820d1 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -137,7 +137,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f8..f67c513548 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -286,7 +286,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e589597..333b4a2b7f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -104,7 +104,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index ae1c129109..7b7fb9eb41 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -127,7 +127,7 @@ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e9..b45c51dc92 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -218,8 +218,8 @@ #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ #define CONFIG_PHY2_ADDR 0x1 #define CONFIG_PHY3_ADDR 0x3 #define CONFIG_ET1011C_PHY 1 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e839..b036d444d1 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -123,7 +123,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/mpc5xx.h b/include/mpc5xx.h index e9b08a0dc7..414651fa0f 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -76,10 +76,10 @@ #define SIUMCR_DBPC01 0x00080000 /* - " - */ #define SIUMCR_DBPC10 0x00100000 /* - " - */ #define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ @@ -90,7 +90,7 @@ #define SIUMCR_MLRC01 0x00000400 /* - " - */ #define SIUMCR_MLRC10 0x00000800 /* - " - */ #define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ +#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control Register @@ -123,13 +123,13 @@ * SCCR - System Clock and reset Control Register */ #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ +#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ #define SCCR_EBDF11 0x00060000 /* reserved */ #define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ @@ -138,11 +138,11 @@ /*----------------------------------------------------------------------- * MC - Memory Controller */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_V 0x00000001 /* Bank valid */ +#define BR_BI 0x00000002 /* Burst inhibit */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ #define BR_LBDIR 0x00000008 /* Late burst data in progess */ #define BR_SETA 0x00000004 /* External Data Acknowledge */ #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ @@ -159,8 +159,8 @@ /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ +#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ +#define UMCR_HSPEED 0x10000000 /* Half speed */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register @@ -174,16 +174,16 @@ * SCI - Serial communication interface */ -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ +#define SCI_TDRE 0x0100 /* Transmit data register empty */ +#define SCI_TE 0x0008 /* Transmitter enabled */ #define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ +#define SCI_RDRF 0x0040 /* Receive data register full */ +#define SCI_PE 0x0400 /* Parity enable */ +#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ +#define SCI_SCXDR_MK 0x00ff /* Data register mask */ #define SCI_M_11 0x0200 /* Frame size is 11 bit */ #define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ +#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ #define SCI_PORT_2 ((int)2) #endif /* __MPC5XX_H__ */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 4bd8863481..30f01d5aa8 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -88,7 +88,7 @@ #define PREP_PCI_MEMORY_BUS 0x80000000 #define PREP_PCI_MEMORY_SIZE 0x80000000 #define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ +#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ #define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ #define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ #define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ @@ -98,8 +98,8 @@ #define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ #define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ #define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ +#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ +#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ #define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ #define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ #define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ diff --git a/include/mpc8260.h b/include/mpc8260.h index b61218ccc2..052529409a 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -664,7 +664,7 @@ #define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ /*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 + * LSDMR - Local Bus SDRAM Mode Register 10-24 */ /* @@ -707,23 +707,23 @@ /*----------------------------------------------------------------------- * TMR1-TMR4 - Timer Mode Registers 17-6 */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ +#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ #define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ +#define TMRx_OM 0x0020 /* Output Mode */ #define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ +#define TMRx_FRR 0x0008 /* Free Run/Restart */ #define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ +#define TMRx_GE 0x0001 /* Gate Enable */ #define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ #define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ #define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ +#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ +#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ #define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ #define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ +#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ /*----------------------------------------------------------------------- diff --git a/include/mpc83xx.h b/include/mpc83xx.h index cbf41c3a93..336c0ac4f2 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -439,9 +439,9 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_MPC831X) -#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 +#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 -#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 +#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 #define HRCWH_RL_EXT_LEGACY 0x00000000 @@ -1218,7 +1218,7 @@ #define FCR_CMD1 0x00FF0000 #define FCR_CMD1_SHIFT 16 #define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 +#define FCR_CMD2_SHIFT 8 #define FCR_CMD3 0x000000FF #define FCR_CMD3_SHIFT 0 @@ -1242,8 +1242,8 @@ /* LTESR - Transfer Error Status Register */ #define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 #define LTESR_WP 0x04000000 #define LTESR_ATMW 0x00800000 #define LTESR_ATMR 0x00400000 diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 11305987f8..bef748f900 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -208,12 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNL001 0x00000100 /* Division by 4 */ -#define SCCR_DFNL010 0x00000200 /* Division by 8 */ -#define SCCR_DFNL011 0x00000300 /* Division by 16 */ -#define SCCR_DFNL100 0x00000400 /* Division by 32 */ -#define SCCR_DFNL101 0x00000500 /* Division by 64 */ -#define SCCR_DFNL110 0x00000600 /* Division by 128 */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ diff --git a/include/ppc405.h b/include/ppc405.h index 6be2a50db7..8e64731929 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -143,12 +143,12 @@ #define UIC_USBH1 0x00040000 /* USB Host 1 */ #define UIC_USBH2 0x00020000 /* USB Host 2 */ #define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ @@ -886,7 +886,7 @@ #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ #define ecr (0xaa) /* edge conditioner register (405gpr) */ @@ -1119,13 +1119,13 @@ | UART Register Offsets '----------------------------------------------------------------------------*/ #define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 +#define DL_LSB 0x00 +#define DL_MSB 0x01 #define INT_ENABLE 0x01 #define FIFO_CONTROL 0x02 #define LINE_CONTROL 0x03 #define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 +#define LINE_STATUS 0x05 #define MODEM_STATUS 0x06 #define SCRATCH 0x07 diff --git a/include/ppc440.h b/include/ppc440.h index 9ba47a53cf..76330f16ac 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -112,7 +112,7 @@ #define icdbtrh 0x39f /* instruction cache debug tag register high */ #define mmucr 0x3b2 /* mmu control register */ #define ccr0 0x3b3 /* core configuration register 0 */ -#define ccr1 0x378 /* core configuration for 440x5 only */ +#define ccr1 0x378 /* core configuration for 440x5 only */ #define icdbdr 0x3d3 /* instruction cache debug data register */ #define dbdr 0x3f3 /* debug data register */ @@ -136,7 +136,7 @@ #define clk_opbd 0x00c0 #define clk_perd 0x00e0 #define clk_mald 0x0100 -#define clk_spcid 0x0120 +#define clk_spcid 0x0120 #define clk_icfg 0x0140 /* 440gx sdr register definations */ @@ -686,8 +686,8 @@ #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 /*-----------------------------------------------------------------------------+ | SDRAM Mode Register -- cgit v1.2.1 From 5a1c9ff0c44305b57cb4d8f9369bba90bcf0e1f8 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 24 Jun 2007 17:23:41 +0200 Subject: ppc4xx: Add pci_pre_init() for 405 boards This patch adds support for calling a plattform dependant pci_pre_init() function for 405 boards. This can be used to move the current pci_405gp_fixup_irq() function into the board code. This patch also makes the CFG_PCI_PRE_INIT define obsolete. A default function with 'weak' attribute is used when a board specific pci_pre_init() is not implemented. Signed-off-by: Matthias Fuchs --- cpu/ppc4xx/405gp_pci.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 8bf03e1b2f..28379298b7 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -77,11 +77,21 @@ #include #include +#ifdef CONFIG_PCI + DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) +/* + * Board-specific pci initialization + * Platform code can reimplement pci_pre_init() if needed + */ +int __pci_pre_init(struct pci_controller *hose) +{ + return 1; +} +int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init"))); -#ifdef CONFIG_PCI +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) #if defined(CONFIG_PMC405) ushort pmc405_pci_subsys_deviceid(void); @@ -191,6 +201,13 @@ void pci_405gp_init(struct pci_controller *hose) if (hose->pci_fb) pciauto_region_init(hose->pci_fb); + /* Let board change/modify hose & do initial checks */ + if (pci_pre_init (hose) == 0) { + printf("PCI: Board-specific initialization failed.\n"); + printf("PCI: Configuration aborted.\n"); + return; + } + pci_register_hose(hose); /*--------------------------------------------------------------------------+ @@ -416,14 +433,12 @@ void pci_init_board(void) #endif -#endif /* CONFIG_PCI */ - #endif /* CONFIG_405GP */ /*-----------------------------------------------------------------------------+ * CONFIG_440 *-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440) && defined(CONFIG_PCI) +#if defined(CONFIG_440) static struct pci_controller ppc440_hose = {0}; @@ -496,14 +511,12 @@ void pci_440_init (struct pci_controller *hose) pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); -#if defined(CFG_PCI_PRE_INIT) /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { printf("PCI: Board-specific initialization failed.\n"); printf("PCI: Configuration aborted.\n"); return; } -#endif pci_register_hose( hose ); @@ -575,4 +588,5 @@ void pci_init_board(void) #endif } -#endif /* CONFIG_440 & CONFIG_PCI */ +#endif /* CONFIG_440 */ +#endif /* CONFIG_PCI */ -- cgit v1.2.1 From 6f35c53166213c24a5a0e2390ed861136ff73870 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 24 Jun 2007 17:41:21 +0200 Subject: ppc4xx: Maintenance patch for esd's CPCI405 derivats -add pci_pre_init() for pci interrupt fixup code -disable phy sleep mode via reset_phy() function -use correct io accessors -cleanup Signed-off-by: Matthias Fuchs --- board/esd/cpci405/cpci405.c | 76 ++++++++++++++++++++++++++++++++------------- include/configs/CPCI405.h | 5 +++ include/configs/CPCI4052.h | 6 ++++ include/configs/CPCI405AB.h | 5 +++ include/configs/CPCI405DT.h | 5 +++ 5 files changed, 76 insertions(+), 21 deletions(-) diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index f80361081a..263b75d3a1 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -23,9 +23,11 @@ #include #include +#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -179,11 +181,15 @@ int board_early_init_f (void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } +#else + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ +#endif mtdcr(uictr, 0x10000000); /* set int trigger levels */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ @@ -227,10 +233,10 @@ int cpci405_version(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -245,7 +251,7 @@ int cpci405_version(void) /* CS2==0 && CS3==1 -> version 2 */ return 2; case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 */ + /* CS2==1 && CS3==0 -> version 3 or 6U board */ return 3; case 0x00000000: /* CS2==0 && CS3==0 -> version 4 */ @@ -283,7 +289,6 @@ int misc_init_r (void) * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ - if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -354,6 +359,7 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; @@ -375,6 +381,7 @@ int misc_init_r (void) udelay(100); *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); } +#endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); @@ -493,12 +500,6 @@ int checkboard (void) #endif putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - return 0; } @@ -511,24 +512,22 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } + /* ------------------------------------------------------------------------- */ #ifdef CONFIG_CPCI405_VER2 @@ -552,6 +551,41 @@ void ide_set_reset(int on) #endif /* CONFIG_CPCI405_VER2 */ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +int pci_pre_init(struct pci_controller *hose) +{ + hose->fixup_irq = cpci405_pci_fixup_irq; + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + + + #ifdef CONFIG_CPCI405AB #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 047e2f1eef..67f7581130 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -55,6 +55,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS | \ @@ -139,6 +143,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d756f447f7..8abdbdc6df 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -56,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -166,6 +171,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 852d94a410..ab6d1168f1 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -57,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -150,6 +154,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 2260327c3f..42ec0801ad 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -56,6 +56,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -171,6 +175,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -- cgit v1.2.1 From 466fff1a7bb5fe764a06450626f6098219f446b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jun 2007 15:57:39 +0200 Subject: ppc4xx: Add pci_pre_init() for 405 boards This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 4 ++-- board/amcc/ebony/ebony.c | 8 ++++---- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/luan/luan.c | 4 ++-- board/amcc/ocotea/ocotea.c | 4 ++-- board/amcc/sequoia/sequoia.c | 17 ++--------------- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yosemite/yosemite.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/esd/cpci405/cpci405.c | 4 ++-- board/lwmon5/lwmon5.c | 4 ++-- board/pcs440ep/pcs440ep.c | 4 ++-- board/prodrive/alpr/alpr.c | 4 ++-- board/prodrive/p3p440/p3p440.c | 4 ++-- board/sandburst/common/sb_common.c | 4 ++-- board/xpedite1k/xpedite1k.c | 4 ++-- doc/README.ppc440 | 13 +++++++------ include/common.h | 9 +++++---- include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 1 - include/configs/XPEDITE1K.h | 1 - include/configs/alpr.h | 1 - include/configs/bamboo.h | 1 - include/configs/ebony.h | 1 - include/configs/katmai.h | 1 - include/configs/luan.h | 1 - include/configs/lwmon5.h | 1 - include/configs/ocotea.h | 1 - include/configs/p3p440.h | 1 - include/configs/pcs440ep.h | 1 - include/configs/sequoia.h | 1 - include/configs/taishan.h | 1 - include/configs/yosemite.h | 1 - include/configs/yucca.h | 1 - 38 files changed, 46 insertions(+), 77 deletions(-) diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 2e651df3b7..caf66909b9 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -416,7 +416,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -457,7 +457,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index dcafac950d..ededb3e7e1 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -207,14 +207,14 @@ long int fixed_sdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; /*--------------------------------------------------------------------------+ - * The ebony board is always configured as the host & requires the - * PCI arbiter to be enabled. + * The ebony board is always configured as the host & requires the + * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ strap = mfdcr(cpc0_strp1); if ((strap & 0x00100000) == 0) { @@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 286bdc1f21..b804d55f2e 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -292,7 +292,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -309,7 +309,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 778aafc766..2eff3b33fd 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -161,7 +161,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init( struct pci_controller *hose ) { unsigned long strap; @@ -179,7 +179,7 @@ int pci_pre_init( struct pci_controller *hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 3f6d2042d7..3bd1b81400 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -306,7 +306,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index ba365aea31..a8966f0e5f 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -426,23 +426,10 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; -#if 0 - /*--------------------------------------------------------------------------+ - * Cactus is always configured as the host & requires the - * PCI arbiter to be enabled ??? - *--------------------------------------------------------------------------*/ - unsigned long strap; - mfsdr(sdr_sdstp1, strap); - if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { - printf("PCI: SDR0_STRP1[PAE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return 0; - } -#endif /*-------------------------------------------------------------------------+ | Set priority for all PLB3 devices to 0. @@ -480,7 +467,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 1a2e53b1ab..bc976c7526 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -236,7 +236,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -253,7 +253,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index c2e12ba12e..912f09ee43 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -385,7 +385,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 90eaab1c80..7316c34b4a 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -604,7 +604,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -621,7 +621,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 263b75d3a1..2ed0fc2722 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -551,7 +551,7 @@ void ide_set_reset(int on) #endif /* CONFIG_CPCI405_VER2 */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line = 0xff; @@ -582,7 +582,7 @@ int pci_pre_init(struct pci_controller *hose) hose->fixup_irq = cpci405_pci_fixup_irq; return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b303ec7cb3..d5b8f8c81b 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -304,7 +304,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -345,7 +345,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 8858f0a5e5..b73ab2adec 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -217,7 +217,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -258,7 +258,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 5abc87dde6..b76449989b 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -172,7 +172,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -192,7 +192,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 2f28e9d87a..1a8aacbdf1 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -176,7 +176,7 @@ int misc_init_r (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; @@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 7816472516..8a831fa35f 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -313,7 +313,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index a569b53472..8411cf06f7 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -209,7 +209,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose ) #endif return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f589f..2e04abacc8 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits diff --git a/include/common.h b/include/common.h index 3c4b37b0dc..d8b6b469e5 100644 --- a/include/common.h +++ b/include/common.h @@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char; #include #include #include -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) #include #endif #if defined(CONFIG_8xx) @@ -248,10 +248,11 @@ void pci_init (void); void pci_init_board(void); void pciinfo (int, int); -#if defined(CONFIG_PCI) && defined(CONFIG_440) -# if defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) int pci_pre_init (struct pci_controller * ); -# endif +#endif + +#if defined(CONFIG_PCI) && defined(CONFIG_440) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 67f7581130..9acde1e6f0 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -143,7 +143,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 8abdbdc6df..3fc99c5024 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -171,7 +171,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index ab6d1168f1..4e2e1a834d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -154,7 +154,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 42ec0801ad..ab302df743 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -175,7 +175,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index fd9bd31627..48b94ee45e 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -263,7 +263,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 148fe9a5c3..7aae2bd143 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -332,7 +332,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 9b32514867..f2ad097db2 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long); #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824d..a7b99f72c0 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -275,7 +275,6 @@ #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_MASTER_INIT diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8e..a1b5682abf 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -389,7 +389,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9ae..70b199218d 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -270,7 +270,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cc47a168ed..a7eda0773b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -314,7 +314,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/luan.h b/include/configs/luan.h index 045a144aad..cbb59c50ea 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -273,7 +273,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267..9bfc0b56a5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -288,7 +288,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fdd..bc8ee1c6f1 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -294,7 +294,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f8..544c1b83de 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -227,7 +227,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e589597..5c73658951 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -267,7 +267,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f..e4f0ac8c9a 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -371,7 +371,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e9..b9936fb155 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -298,7 +298,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e839..6e01244008 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -312,7 +312,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 7f8b0228ae..1fdcc4b505 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -289,7 +289,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT -- cgit v1.2.1 From 807018fb7faceb429ce0cb47baa2073746b33a4e Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Mon, 25 Jun 2007 16:50:55 +0200 Subject: ppc4xx: Fix O=buildir builds This patch fixes the problem to assemble cpu/ppc4xx/start.S experienced last week where building failed having specified O=../build.sequoia. Signed-off-by: Niklaus Giger --- cpu/ppc4xx/config.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index e7fc3f636e..4fd510899c 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -24,7 +24,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float -cfg=$(shell grep configs $(TOPDIR)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) ifneq (,$(findstring CONFIG_440,$(is440))) -- cgit v1.2.1 From a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Mon, 25 Jun 2007 17:03:13 +0200 Subject: ppc4xx: PPC440EPx Emit DDR0 registers on machine check interrupt This patch prints the DDR status registers upon machine check interrupt on the 440EPx/GRx. This can be useful especially when ECC support is enabled. I added some small changes to the original patch from Niklaus to make it compile clean. Signed-off-by: Niklaus Giger Signed-off-by: Stefan Roese --- cpu/ppc4xx/traps.c | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) mode change 100644 => 100755 cpu/ppc4xx/traps.c diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c old mode 100644 new mode 100755 index 7c44a2990b..eb9420e57a --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -145,6 +145,9 @@ void MachineCheckException(struct pt_regs *regs) { unsigned long fixup, val; +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + u32 value2; +#endif /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to @@ -203,7 +206,89 @@ MachineCheckException(struct pt_regs *regs) /* Clear MCSR */ mtspr(SPRN_MCSR, val); } -#endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + mfsdram(DDR0_00, val) ; + printf("DDR0: DDR0_00 %p\n", val); + val = (val >> 16) & 0xff; + if (val & 0x80) + printf("DDR0: At least one interrupt active\n"); + if (val & 0x40) + printf("DDR0: DRAM initialization complete.\n"); + if (val & 0x20) + printf("DDR0: Multiple uncorrectable ECC events.\n"); + if (val & 0x10) + printf("DDR0: Single uncorrectable ECC event.\n"); + if (val & 0x08) + printf("DDR0: Multiple correctable ECC events.\n"); + if (val & 0x04) + printf("DDR0: Single correctable ECC event.\n"); + if (val & 0x02) + printf("Multiple accesses outside the defined" + " physical memory space detected\n"); + if (val & 0x01) + printf("DDR0: Single access outside the defined" + " physical memory space detected.\n"); + + mfsdram(DDR0_01, val); + val = (val >> 8) & 0x7; + switch (val ) { + case 0: + printf("DDR0: Write Out-of-Range command\n"); + break; + case 1: + printf("DDR0: Read Out-of-Range command\n"); + break; + case 2: + printf("DDR0: Masked write Out-of-Range command\n"); + break; + case 4: + printf("DDR0: Wrap write Out-of-Range command\n"); + break; + case 5: + printf("DDR0: Wrap read Out-of-Range command\n"); + break; + default: + mfsdram(DDR0_01, value2); + printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2); + } + mfsdram(DDR0_23, val); + if ( (val >> 16) & 0xff) + printf("DDR0: Syndrome for correctable ECC event 0x%x\n", + (val >> 16) & 0xff); + mfsdram(DDR0_23, val); + if ( (val >> 8) & 0xff) + printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n", + (val >> 8) & 0xff); + mfsdram(DDR0_33, val); + if (val) + printf("DDR0: Address of command that caused an " + "Out-of-Range interrupt %p\n", val); + mfsdram(DDR0_34, val); + if (val) + printf("DDR0: Address of uncorrectable ECC event %p\n", val); + mfsdram(DDR0_35, val); + if (val) + printf("DDR0: Address of uncorrectable ECC event %p\n", val); + mfsdram(DDR0_36, val); + if (val) + printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + mfsdram(DDR0_37, val); + if (val) + printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val); + mfsdram(DDR0_38, val); + if (val) + printf("DDR0: Address of correctable ECC event %p\n", val); + mfsdram(DDR0_39, val); + if (val) + printf("DDR0: Address of correctable ECC event %p\n", val); + mfsdram(DDR0_40, val); + if (val) + printf("DDR0: Data of correctable ECC event 0x%08x\n", val); + mfsdram(DDR0_41, val); + if (val) + printf("DDR0: Data of correctable ECC event 0x%08x\n", val); +#endif /* CONFIG_440EPX */ +#endif /* CONFIG_440 */ show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("machine check"); -- cgit v1.2.1 From 1f2a05898658900dc5717761e27abf2052e67e13 Mon Sep 17 00:00:00 2001 From: Mushtaq Khan Date: Sat, 30 Jun 2007 18:50:48 +0200 Subject: Fix S-ATA support. Signed-off-by: mushtaq khan --- common/cmd_sata.c | 8 ++++---- include/sata.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 2e601a7d80..bd4c11fd9b 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -375,9 +375,9 @@ msleep (int count) } ulong -sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff) { - ulong n = 0; + ulong n = 0, *buffer = (ulong *)buff; u8 dev = 0, num = 0, mask = 0, status = 0; #ifdef CONFIG_LBA48 @@ -482,9 +482,9 @@ sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) } ulong -sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff) { - ulong n = 0; + ulong n = 0, *buffer = (ulong *)buff; unsigned char status = 0, num = 0, dev = 0, mask = 0; #ifdef CONFIG_LBA48 diff --git a/include/sata.h b/include/sata.h index a8713f817e..165b471b28 100644 --- a/include/sata.h +++ b/include/sata.h @@ -28,8 +28,8 @@ struct sata_port { struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /* 1-port is present and */ - 0-port is not available */ + unsigned char port_state; /* 1-port is available and */ + /* 0-port is not available */ unsigned char dev_mask; }; @@ -74,18 +74,18 @@ int sata_devchk (struct sata_ioports *ioaddr, int dev); void dev_select (struct sata_ioports *ioaddr, int dev); u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); u8 sata_chk_status (struct sata_ioports *ioaddr); -ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); -ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer); +ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer); void msleep (int count); #else extern int sata_bus_softreset (int num); extern void sata_identify (int num, int dev); extern void sata_port (struct sata_ioports *ioport); extern void set_Feature_cmd (int num, int dev); -extern ulong sata_read (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); -extern ulong sata_write (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); +extern ulong sata_read (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); +extern ulong sata_write (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); extern void msleep (int count); #endif -- cgit v1.2.1