From cb1629f91a487e34284868a2d246bc3b122c6395 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Apr 2016 09:56:48 -0700 Subject: powerpc: Disable flush or invalidate dcache by range for some SoCs Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun --- arch/powerpc/lib/ppccache.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S index b96dbc60e0..66cf02dbd0 100644 --- a/arch/powerpc/lib/ppccache.S +++ b/arch/powerpc/lib/ppccache.S @@ -65,6 +65,7 @@ ppcSync: * flush_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(flush_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -77,6 +78,7 @@ _GLOBAL(flush_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbst's to get to ram */ +#endif blr /* @@ -87,6 +89,7 @@ _GLOBAL(flush_dcache_range) * invalidate_dcache_range(unsigned long start, unsigned long stop) */ _GLOBAL(invalidate_dcache_range) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx) li r5,L1_CACHE_BYTES-1 andc r3,r3,r5 subf r4,r3,r4 @@ -100,5 +103,6 @@ _GLOBAL(invalidate_dcache_range) addi r3,r3,L1_CACHE_BYTES bdnz 1b sync /* wait for dcbi's to get to ram */ +#endif blr -- cgit v1.2.1 From a4d3074209f84038c488b3015d494ff1bb8bb7ee Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Apr 2016 09:53:27 -0700 Subject: powerpc/t208xqds: Update MAINTAINERS file Signed-off-by: York Sun CC: Shengzhou Liu --- board/freescale/t208xqds/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS index deda092a6a..d747de3f34 100644 --- a/board/freescale/t208xqds/MAINTAINERS +++ b/board/freescale/t208xqds/MAINTAINERS @@ -1,5 +1,5 @@ T208XQDS BOARD -#M: - +M: Shengzhou Liu S: Maintained F: board/freescale/t208xqds/ F: include/configs/T208xQDS.h -- cgit v1.2.1 From 9272611e991d6be1c5f53f3ef8a580513ff65a39 Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Apr 2016 09:53:28 -0700 Subject: powerpc/t208xrdb: Update MAINTAINERS file Signed-off-by: York Sun CC: Shengzhou Liu --- board/freescale/t208xrdb/MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS index 16428798cd..ccbfbab142 100644 --- a/board/freescale/t208xrdb/MAINTAINERS +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -1,5 +1,5 @@ T208XRDB BOARD -#M: - +M: Shengzhou Liu S: Maintained F: board/freescale/t208xrdb/ F: include/configs/T208xRDB.h -- cgit v1.2.1 From 46caebc1dff8f456b4f076bbebbb2ba32236d06d Mon Sep 17 00:00:00 2001 From: York Sun Date: Thu, 7 Apr 2016 09:52:11 -0700 Subject: powerpc/t2080qds: Enable qixis commands to reboot from NAND and SD Signed-off-by: York Sun CC: Shengzhou Liu --- include/configs/T208xQDS.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d8c57a833b..f48697c033 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -291,6 +291,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_RCW_SRC_NAND 0x104 +#define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x83 #define QIXIS_RST_FORCE_MEM 0x1 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -- cgit v1.2.1 From 82eda68444fa4d026bcf1f59c7c0d044ddbcb193 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Mon, 18 Apr 2016 22:58:33 +0530 Subject: powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun --- arch/powerpc/cpu/mpc85xx/start.S | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 82a151a0d0..4c51225868 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -720,16 +720,39 @@ enable_l2_cluster_l2: ori r4, r4, (L2CSR0_L2FI|L2CSR0_L2LFC)@l sync stw r4, 0(r3) /* invalidate L2 */ + /* Poll till the bits are cleared */ 1: sync lwz r0, 0(r3) twi 0, r0, 0 isync and. r1, r0, r4 bne 1b + + /* L2PE must be set before L2 cache is enabled */ + lis r4, (L2CSR0_L2PE)@h + ori r4, r4, (L2CSR0_L2PE)@l + sync + stw r4, 0(r3) /* enable L2 parity/ECC error checking */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + lis r4, (L2CSR0_L2E|L2CSR0_L2PE)@h ori r4, r4, (L2CSR0_L2REP_MODE)@l sync stw r4, 0(r3) /* enable L2 */ + /* Poll till the bit is set */ +1: sync + lwz r0, 0(r3) + twi 0, r0, 0 + isync + and. r1, r0, r4 + beq 1b + delete_ccsr_l2_tlb: delete_tlb0_entry 0, CONFIG_SYS_CCSRBAR + 0xC20000, MAS2_I|MAS2_G, r3 #endif -- cgit v1.2.1 From d1fc8ed485cbf44434a9bc2a02ddf2a94f2183c1 Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Thu, 21 Apr 2016 14:23:46 +0800 Subject: powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDB Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang Acked-by: Joe Hershberger Reviewed-by: York Sun --- board/freescale/t4rdb/eth.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index e563a6169a..ae2451e4ba 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -77,6 +77,9 @@ int board_eth_init(bd_t *bis) puts("Invalid SerDes1 protocol for T4240RDB\n"); } + fm_disable_port(FM1_DTSEC5); + fm_disable_port(FM1_DTSEC6); + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { @@ -115,6 +118,8 @@ int board_eth_init(bd_t *bis) puts("Invalid SerDes2 protocol for T4240RDB\n"); } + fm_disable_port(FM2_DTSEC5); + fm_disable_port(FM2_DTSEC6); for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { interface = fm_info_get_enet_if(i); switch (interface) { -- cgit v1.2.1 From 8ef548d5f13e68e1b3975d9b68920bfa8bf09891 Mon Sep 17 00:00:00 2001 From: Ying Zhang Date: Mon, 18 Apr 2016 17:04:16 +0800 Subject: powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in some case When using rcw protocols to support 10G on MAC9 and MAC10, these MACs should not be identified as 1G interface, otherwise, one MAC will be listed as two Ethernet ports. For example, MAC9 will be listed as FM1@TGEC1 and FM1@DTSEC9. Signed-off-by: Ying Zhang Reviewed-by: York Sun --- drivers/net/fm/t4240.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index ae5aca4bb4..70887fa45f 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -74,7 +74,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if ((port == FM1_DTSEC9 || port == FM1_DTSEC10) && ((is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)))) - return PHY_INTERFACE_MODE_XGMII; + return PHY_INTERFACE_MODE_NONE; if ((port == FM2_10GEC1 || port == FM2_10GEC2) && ((is_serdes_configured(XAUI_FM2_MAC9)) || -- cgit v1.2.1