From 5902f4ce0f2bd1411e40dc0ece3598a0fc19b2ae Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Mon, 9 Mar 2015 17:12:01 -0500 Subject: ARM: Introduce erratum workaround for 430973 430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon Tested-by: Matt Porter Reviewed-by: Tom Rini --- README | 1 + arch/arm/cpu/armv7/start.S | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/README b/README index c3226386cf..360f2a9f70 100644 --- a/README +++ b/README @@ -693,6 +693,7 @@ The following options need to be configured: NOTE: The following can be machine specific errata. These do have ability to provide rudimentary version and machine specific checks, but expect no product checks. + CONFIG_ARM_ERRATA_430973 CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_798870 diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 8483687879..41fb24cf32 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -200,6 +200,19 @@ skip_errata_798870: pop {r1-r5} @ Restore the cpu info - fall through skip_errata_454179: +#endif + +#ifdef CONFIG_ARM_ERRATA_430973 + cmp r2, #0x21 @ Only on < r2p1 + bge skip_errata_430973 + + mrc p15, 0, r0, c1, c0, 1 @ Read ACR + orr r0, r0, #(0x1 << 6) @ Set IBE bit + push {r1-r5} @ Save the cpu info registers + bl v7_arch_cp15_set_acr + pop {r1-r5} @ Restore the cpu info - fall through + +skip_errata_430973: #endif mov pc, r5 @ back to my caller -- cgit v1.2.1