From b699b01e5cf0f74f123dcc7090df232214dddf93 Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Tue, 21 Oct 2014 13:51:58 +0800 Subject: arm: ls102xa: fixed a bus frequency setting error The bus frequency in SOC node should be clock frequency of platform. That is not true if it is devided by 2. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 4ce38086f4..989780d273 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -91,7 +91,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) } do_fixup_by_prop_u32(blob, "device_type", "soc", - 4, "bus-frequency", busclk / 2, 1); + 4, "bus-frequency", busclk, 1); ft_fixup_enet_phy_connect_type(blob); -- cgit v1.2.1 From 306fa012794e68e568bd51b829d1754323e0b8aa Mon Sep 17 00:00:00 2001 From: chenhui zhao Date: Wed, 22 Oct 2014 18:20:22 +0800 Subject: arm: ls102xa: clear EPU registers for deep sleep After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 57 +++++++++++++++++++++++++ arch/arm/cpu/armv7/ls102xa/fsl_epu.h | 68 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/config.h | 1 + 5 files changed, 143 insertions(+) create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.c create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.h diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index d82ce8d014..ae4f25dcd3 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -7,6 +7,7 @@ obj-y += cpu.o obj-y += clock.o obj-y += timer.o +obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index b7dde45ed3..fae6c68efc 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -12,6 +12,8 @@ #include #include +#include "fsl_epu.h" + DECLARE_GLOBAL_DATA_PTR; #if defined(CONFIG_DISPLAY_CPUINFO) @@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis) return 0; } + +int arch_cpu_init(void) +{ + void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); + + /* + * After wakeup from deep sleep, Clear EPU registers + * as early as possible to prevent from possible issue. + * It's also safe to clear at normal boot. + */ + fsl_epu_clean(epu_base); + + return 0; +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c new file mode 100644 index 0000000000..6212640d14 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c @@ -0,0 +1,57 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "fsl_epu.h" + +/** + * fsl_epu_clean - Clear EPU registers + */ +void fsl_epu_clean(void *epu_base) +{ + u32 offset; + + /* follow the exact sequence to clear the registers */ + /* Clear EPACRn */ + for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPEVTCRn */ + for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPGCR */ + out_be32(epu_base + EPGCR, 0); + + /* Clear EPSMCRn */ + for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCCRn */ + for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCMPRn */ + for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPCTRn */ + for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPIMCRn */ + for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE) + out_be32(epu_base + offset, 0); + + /* Clear EPXTRIGCRn */ + out_be32(epu_base + EPXTRIGCR, 0); + + /* Clear EPECRn */ + for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE) + out_be32(epu_base + offset, 0); +} diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h new file mode 100644 index 0000000000..d658aad2ea --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h @@ -0,0 +1,68 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_EPU_H +#define __FSL_EPU_H + +#include + +#define FSL_STRIDE_4B 4 +#define FSL_STRIDE_8B 8 + +/* Block offsets */ +#define EPU_BLOCK_OFFSET 0x00000000 + +/* EPGCR (Event Processor Global Control Register) */ +#define EPGCR 0x000 + +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */ +#define EPEVTCR0 0x050 +#define EPEVTCR9 0x074 +#define EPEVTCR_STRIDE FSL_STRIDE_4B + +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */ +#define EPXTRIGCR 0x090 + +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */ +#define EPIMCR0 0x100 +#define EPIMCR31 0x17C +#define EPIMCR_STRIDE FSL_STRIDE_4B + +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */ +#define EPSMCR0 0x200 +#define EPSMCR15 0x278 +#define EPSMCR_STRIDE FSL_STRIDE_8B + +/* EPECR0-15 (Event Processor Event Control Registers) */ +#define EPECR0 0x300 +#define EPECR15 0x33C +#define EPECR_STRIDE FSL_STRIDE_4B + +/* EPACR0-15 (Event Processor Action Control Registers) */ +#define EPACR0 0x400 +#define EPACR15 0x43C +#define EPACR_STRIDE FSL_STRIDE_4B + +/* EPCCRi0-15 (Event Processor Counter Control Registers) */ +#define EPCCR0 0x800 +#define EPCCR15 0x83C +#define EPCCR31 0x87C +#define EPCCR_STRIDE FSL_STRIDE_4B + +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */ +#define EPCMPR0 0x900 +#define EPCMPR15 0x93C +#define EPCMPR31 0x97C +#define EPCMPR_STRIDE FSL_STRIDE_4B + +/* EPCTR0-31 (Event Processor Counter Register) */ +#define EPCTR0 0xA00 +#define EPCTR31 0xA7C +#define EPCTR_STRIDE FSL_STRIDE_4B + +void fsl_epu_clean(void *epu_base); + +#endif diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ba86eea040..7d70c7bcbf 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -13,6 +13,7 @@ #define OCRAM_SIZE 0x00020000 #define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) -- cgit v1.2.1 From da419027afe8336284f5db9867a880dfb3b3ab26 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Fri, 31 Oct 2014 13:43:44 +0800 Subject: arm: ls102xa: Update PCIe dts node status The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol. Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 3 ++ arch/arm/include/asm/pcie_layerscape.h | 13 ++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 5 +++ board/freescale/ls1021atwr/ls1021atwr.c | 5 +++ drivers/pci/Makefile | 1 + drivers/pci/pcie_layerscape.c | 51 ++++++++++++++++++++++++++++++ include/configs/ls1021aqds.h | 8 +++++ include/configs/ls1021atwr.h | 7 ++++ 8 files changed, 93 insertions(+) create mode 100644 arch/arm/include/asm/pcie_layerscape.h create mode 100644 drivers/pci/pcie_layerscape.c diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 7d70c7bcbf..704d683e83 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -53,6 +53,9 @@ #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000000..fb08578f10 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 0a7720a001..d7813d90c0 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -258,6 +259,10 @@ int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + return 0; } diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 3e8c37b05d..269d3e2c51 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -307,6 +308,10 @@ int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif + return 0; } diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 55d6a9b322..85e82bdb8c 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c new file mode 100644 index 0000000000..291c249c86 --- /dev/null +++ b/drivers/pci/pcie_layerscape.c @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_BOARD_SETUP +#include +#include + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +void ft_pcie_setup(void *blob, bd_t *bd) +{ + #ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); + #endif + + #ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); + #endif +} + +#else +void ft_pcie_setup(void *blob, bd_t *bd) +{ +} +#endif + +void pci_init_board(void) +{ +} diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 48e10ec8c4..a8383f1888 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -341,6 +341,14 @@ unsigned long get_board_ddr_clk(void); #endif #endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3eac7eea01..b5ecde389a 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -236,6 +236,13 @@ #define CONFIG_HAS_ETH2 #endif +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- cgit v1.2.1 From afff13790e38eea6378801616b1749464f796ad3 Mon Sep 17 00:00:00 2001 From: Chenhui Zhao Date: Thu, 6 Nov 2014 10:51:59 +0800 Subject: ls1021aqds: set the default I2C channel before DDR init When resuming from deep sleep, the I2C channel may not be in the default channel. So, switch to the default channel before accessing DDR SPD. Signed-off-by: Chenhui Zhao Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index d7813d90c0..bf22fced9c 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -102,8 +102,27 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + int dram_init(void) { + /* + * When resuming from deep sleep, the I2C channel may not be + * in the default channel. So, switch to the default channel + * before accessing DDR SPD. + */ + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); gd->ram_size = initdram(0); return 0; @@ -122,19 +141,6 @@ int board_mmc_init(bd_t *bis) } #endif -int select_i2c_ch_pca9547(u8 ch) -{ - int ret; - - ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); - if (ret) { - puts("PCA: failed to select proper channel\n"); - return ret; - } - - return 0; -} - int board_early_init_f(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; -- cgit v1.2.1 From 94cb17d0786867b8bffb684adb48f7111d9d5b63 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:41 +0800 Subject: ls102xa: pblimage: Add pblimage tool support for LS102xA For LS102xA, the size of spl/u-boot-spl.bin is variable. This patch adds the support to deal with the variable u-boot size in pblimage tool. It will be padded to 64 byte boundary. Use pblimage_check_params() to add the specific operations for ARM, such as PBI CRC and END command and the calculation of pbl_cmd_initaddr. Signed-off-by: Alison Wang Reviewed-by: York Sun --- Makefile | 3 +- tools/pblimage.c | 110 +++++++++++++++++++++++++++++++++++++------------------ 2 files changed, 77 insertions(+), 36 deletions(-) diff --git a/Makefile b/Makefile index 2308828fb9..d3e99e5865 100644 --- a/Makefile +++ b/Makefile @@ -999,7 +999,8 @@ u-boot-img.bin: spl/u-boot-spl.bin u-boot.img FORCE #concatenated with u-boot binary. It is need by PowerPC SoC having #internal SRAM <= 512KB. MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ - -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage + -R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage \ + -A $(ARCH) -a $(CONFIG_SPL_TEXT_BASE) spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/tools/pblimage.c b/tools/pblimage.c index 6e6e801314..2a799ab4b6 100644 --- a/tools/pblimage.c +++ b/tools/pblimage.c @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012-2014 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,6 +8,10 @@ #include "pblimage.h" #include "pbl_crc32.h" +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define PBL_ACS_CONT_CMD 0x81000000 +#define PBL_ADDR_24BIT_MASK 0x00ffffff + /* * Initialize to an invalid value. */ @@ -22,6 +26,13 @@ static int pbl_size; static char *fname = "Unknown"; static int lineno = -1; static struct pbl_header pblimage_header; +static int uboot_size; +static int arch_flag; + +static uint32_t pbl_cmd_initaddr; +static uint32_t pbi_crc_cmd1; +static uint32_t pbi_crc_cmd2; +static uint32_t pbl_end_cmd[4]; static union { @@ -38,20 +49,6 @@ static union * start offset by subtracting the size of the u-boot image from the * top of the allowable 24-bit range. */ -static void init_next_pbl_cmd(FILE *fp_uboot) -{ - struct stat st; - int fd = fileno(fp_uboot); - - if (fstat(fd, &st) == -1) { - printf("Error: Could not determine u-boot image size. %s\n", - strerror(errno)); - exit(EXIT_FAILURE); - } - - next_pbl_cmd = 0x82000000 - st.st_size; -} - static void generate_pbl_cmd(void) { uint32_t val = next_pbl_cmd; @@ -66,11 +63,15 @@ static void generate_pbl_cmd(void) static void pbl_fget(size_t size, FILE *stream) { - unsigned char c; + unsigned char c = 0xff; int c_temp; - while (size && (c_temp = fgetc(stream)) != EOF) { - c = (unsigned char)c_temp; + while (size) { + c_temp = fgetc(stream); + if (c_temp != EOF) + c = (unsigned char)c_temp; + else if ((c_temp == EOF) && (arch_flag == IH_ARCH_ARM)) + c = 0xff; *pmem_buf++ = c; pbl_size++; size--; @@ -80,8 +81,8 @@ static void pbl_fget(size_t size, FILE *stream) /* load split u-boot with PBI command 81xxxxxx. */ static void load_uboot(FILE *fp_uboot) { - init_next_pbl_cmd(fp_uboot); - while (next_pbl_cmd < 0x82000000) { + next_pbl_cmd = pbl_cmd_initaddr - uboot_size; + while (next_pbl_cmd < pbl_cmd_initaddr) { generate_pbl_cmd(); pbl_fget(64, fp_uboot); } @@ -154,8 +155,6 @@ static uint32_t reverse_byte(uint32_t val) /* write end command and crc command to memory. */ static void add_end_cmd(void) { - uint32_t pbl_end_cmd[4] = {0x09138000, 0x00000000, - 0x091380c0, 0x00000000}; uint32_t crc32_pbl; int i; unsigned char *p = (unsigned char *)&pbl_end_cmd; @@ -172,8 +171,8 @@ static void add_end_cmd(void) /* Add PBI CRC command. */ *pmem_buf++ = 0x08; - *pmem_buf++ = 0x13; - *pmem_buf++ = 0x80; + *pmem_buf++ = pbi_crc_cmd1; + *pmem_buf++ = pbi_crc_cmd2; *pmem_buf++ = 0x40; pbl_size += 4; @@ -184,17 +183,6 @@ static void add_end_cmd(void) *pmem_buf++ = (crc32_pbl >> 8) & 0xff; *pmem_buf++ = (crc32_pbl) & 0xff; pbl_size += 4; - - if ((pbl_size % 16) != 0) { - for (i = 0; i < 8; i++) { - *pmem_buf++ = 0x0; - pbl_size++; - } - } - if ((pbl_size % 16 != 0)) { - printf("Error: Bad size of image file\n"); - exit(EXIT_FAILURE); - } } void pbl_load_uboot(int ifd, struct image_tool_params *params) @@ -268,12 +256,64 @@ static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, /*nothing need to do, pbl_load_uboot takes care of whole file. */ } +int pblimage_check_params(struct image_tool_params *params) +{ + FILE *fp_uboot; + int fd; + struct stat st; + + if (!params) + return EXIT_FAILURE; + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + fd = fileno(fp_uboot); + + if (fstat(fd, &st) == -1) { + printf("Error: Could not determine u-boot image size. %s\n", + strerror(errno)); + exit(EXIT_FAILURE); + } + + /* For the variable size, we need to pad it to 64 byte boundary */ + uboot_size = roundup(st.st_size, 64); + + if (params->arch == IH_ARCH_ARM) { + arch_flag = IH_ARCH_ARM; + pbi_crc_cmd1 = 0x61; + pbi_crc_cmd2 = 0; + pbl_cmd_initaddr = params->addr & PBL_ADDR_24BIT_MASK; + pbl_cmd_initaddr |= PBL_ACS_CONT_CMD; + pbl_cmd_initaddr |= uboot_size; + pbl_end_cmd[0] = 0x09610000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x096100c0; + pbl_end_cmd[3] = 0x00000000; + } else if (params->arch == IH_ARCH_PPC) { + arch_flag = IH_ARCH_PPC; + pbi_crc_cmd1 = 0x13; + pbi_crc_cmd2 = 0x80; + pbl_cmd_initaddr = 0x82000000; + pbl_end_cmd[0] = 0x09138000; + pbl_end_cmd[1] = 0x00000000; + pbl_end_cmd[2] = 0x091380c0; + pbl_end_cmd[3] = 0x00000000; + } + + next_pbl_cmd = pbl_cmd_initaddr; + return 0; +}; + /* pblimage parameters */ static struct image_type_params pblimage_params = { .name = "Freescale PBL Boot Image support", .header_size = sizeof(struct pbl_header), .hdr = (void *)&pblimage_header, .check_image_type = pblimage_check_image_types, + .check_params = pblimage_check_params, .verify_header = pblimage_verify_header, .print_header = pblimage_print_header, .set_header = pblimage_set_header, -- cgit v1.2.1 From 45c2e480edd5360c46f92bfb7e8ca6ac4554767f Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:42 +0800 Subject: spl: Use u-boot.img instead of u-boot.bin In SD boot, the magic number of u-boot image will be checked. For LS102xA, u-boot.bin doesn't have the magic number. So use u-boot.img which includes the magic number instead of u-boot.bin when producing u-boot-with-spl-pbl.bin. Signed-off-by: Alison Wang Reviewed-by: York Sun --- Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index d3e99e5865..63eccc2364 100644 --- a/Makefile +++ b/Makefile @@ -1005,10 +1005,16 @@ MKIMAGEFLAGS_u-boot-spl.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) +ifeq ($(ARCH),arm) +UBOOT_BINLOAD := u-boot.img +else +UBOOT_BINLOAD := u-boot.bin +endif + OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ --gap-fill=0xff -u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl u-boot.bin FORCE +u-boot-with-spl-pbl.bin: spl/u-boot-spl.pbl $(UBOOT_BINLOAD) FORCE $(call if_changed,pad_cat) # PPC4xx needs the SPL at the end of the image, since the reset vector -- cgit v1.2.1 From 14d54dec1ba55d1b12c1fe17855d2ec5fd69734e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:43 +0800 Subject: arm: spl: Add I2C linker list in generic .lds On LS1, DDR is initialized by reading SPD through I2C interface in SPL code. For I2C, ll_entry_count() is called, and it returns the number of elements of a linker-generated array placed into subsection of .u_boot_list section specified by _list argument. So add I2C linker list in the generic .lds to fix the issue about using I2C in SPL. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/cpu/u-boot-spl.lds | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index a69b0061d2..a8be204038 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -32,6 +32,9 @@ SECTIONS } . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*_i2c_*))); + } . = .; #ifdef CONFIG_SPL_DM -- cgit v1.2.1 From 50f0c6632527cbdc3c67f60a7f51ccba2564b567 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:45 +0800 Subject: kconfig: ls1021a: add SUPPORT_SPL Add SUPPORT_SPL feature for SD and NAND boot on LS1021AQDS and LS1021ATWR. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7a64b665c6..11ae5f8b6c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -730,10 +730,12 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool "Support ls1021aqds_nor" select CPU_V7 + select SUPPORT_SPL config TARGET_LS1021ATWR bool "Support ls1021atwr_nor" select CPU_V7 + select SUPPORT_SPL config TARGET_BALLOON3 bool "Support balloon3" -- cgit v1.2.1 From 2565d18de0c57d95b32686f11aa98fd40d8a7e26 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:46 +0800 Subject: ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macro Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: Jason Jin Signed-off-by: Alison Wang Reviewed-by: York Sun --- board/freescale/common/qixis.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index d8fed14ce9..52d20219ec 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -100,8 +100,15 @@ u8 qixis_read_i2c(unsigned int reg); void qixis_write_i2c(unsigned int reg, u8 value); #endif +#if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) +#define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) +#define QIXIS_WRITE(reg, value) \ + qixis_write_i2c(offsetof(struct qixis, reg), value) +#else #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) #define QIXIS_WRITE_I2C(reg, value) \ -- cgit v1.2.1 From 86949c2b7c94542c20767c405fc458346bd3975b Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:47 +0800 Subject: arm: ls102xa: Add SD boot support for LS1021AQDS board This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/Makefile | 1 + arch/arm/cpu/armv7/ls102xa/spl.c | 33 ++++++++++++++++++++ arch/arm/include/asm/arch-ls102xa/spl.h | 20 ++++++++++++ board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021aqds/ddr.c | 5 ++- board/freescale/ls1021aqds/ls1021aqds.c | 39 +++++++++++++++++++++++ board/freescale/ls1021aqds/ls102xa_pbi.cfg | 12 +++++++ board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg | 14 +++++++++ configs/ls1021aqds_sdcard_defconfig | 4 +++ include/configs/ls1021aqds.h | 45 +++++++++++++++++++++++++++ 10 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/ls102xa/spl.c create mode 100644 arch/arm/include/asm/arch-ls102xa/spl.h create mode 100644 board/freescale/ls1021aqds/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021aqds_sdcard_defconfig diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index ae4f25dcd3..2e6a20757f 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -11,3 +11,4 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o +obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/spl.c b/arch/arm/cpu/armv7/ls102xa/spl.c new file mode 100644 index 0000000000..1dfbf54802 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/spl.c @@ -0,0 +1,33 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SPL_MMC_SUPPORT + return BOOT_DEVICE_MMC1; +#endif + return BOOT_DEVICE_NAND; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { + case BOOT_DEVICE_MMC1: +#ifdef CONFIG_SPL_FAT_SUPPORT + return MMCSD_MODE_FAT; +#else + return MMCSD_MODE_RAW; +#endif + case BOOT_DEVICE_NAND: + return 0; + default: + puts("spl: error: unsupported device\n"); + hang(); + } +} diff --git a/arch/arm/include/asm/arch-ls102xa/spl.h b/arch/arm/include/asm/arch-ls102xa/spl.h new file mode 100644 index 0000000000..26e4ea134b --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/spl.h @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_SPL_H__ +#define __ASM_ARCH_SPL_H__ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_XIPWAIT 2 +#define BOOT_DEVICE_NAND 3 +#define BOOT_DEVICE_ONENAND 4 +#define BOOT_DEVICE_MMC1 5 +#define BOOT_DEVICE_MMC2 6 +#define BOOT_DEVICE_MMC2_2 7 +#define BOOT_DEVICE_SPI 10 + +#endif /* __ASM_ARCH_SPL_H__ */ diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index e30e94471b..962176b533 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/ls1021aqds.h F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig +F: configs/ls1021aqds_sdcard_defconfig diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c index 5898e33744..a539ff9791 100644 --- a/board/freescale/ls1021aqds/ddr.c +++ b/board/freescale/ls1021aqds/ddr.c @@ -153,9 +153,12 @@ phys_size_t initdram(int board_type) { phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL) puts("Initializing DDR....using SPD\n"); dram_size = fsl_ddr_sdram(); - +#else + dram_size = fsl_ddr_sdram_size(); +#endif return dram_size; } diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index bf22fced9c..9eab42d6c7 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "../common/qixis.h" #include "ls1021aqds_qixis.h" @@ -34,10 +35,17 @@ enum { int checkboard(void) { char buf[64]; +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; +#endif puts("Board: LS1021AQDS\n"); +#ifdef CONFIG_SD_BOOT + puts("SD\n"); +#elif CONFIG_QSPI_BOOT + puts("QSPI\n"); +#else sw = QIXIS_READ(brdcfg[0]); sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; @@ -51,6 +59,7 @@ int checkboard(void) printf("IFCCard\n"); else printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); +#endif printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); @@ -165,6 +174,36 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + get_clocks(); + + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + i2c_init_all(); +#endif + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int config_board_mux(int ctrl_type) { u8 reg12; diff --git a/board/freescale/ls1021aqds/ls102xa_pbi.cfg b/board/freescale/ls1021aqds/ls102xa_pbi.cfg new file mode 100644 index 0000000000..f1a1b63ab7 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000000..9d99bd862d --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +60000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#60000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20024800 001b7200 00000000 00000000 diff --git a/configs/ls1021aqds_sdcard_defconfig b/configs/ls1021aqds_sdcard_defconfig new file mode 100644 index 0000000000..e03c3b467d --- /dev/null +++ b/configs/ls1021aqds_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index a8383f1888..4a2e6098b9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -40,6 +40,39 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -356,6 +389,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + #define CONFIG_CMD_IMLS #define CONFIG_HWCONFIG @@ -404,17 +438,28 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif /* * Environment */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP -- cgit v1.2.1 From 8415bb68c8c2e0430f58fc349352a565bddf286e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 15:00:48 +0800 Subject: arm: ls102xa: Add SD boot support for LS1021ATWR board This patch adds SD boot support for LS1021ATWR board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Chen Lu Signed-off-by: Alison Wang Signed-off-by: Jason Jin Reviewed-by: York Sun --- board/freescale/ls1021atwr/MAINTAINERS | 1 + board/freescale/ls1021atwr/ls1021atwr.c | 20 ++++++++++++ board/freescale/ls1021atwr/ls102xa_pbi.cfg | 12 ++++++++ board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg | 14 +++++++++ configs/ls1021atwr_sdcard_defconfig | 4 +++ include/configs/ls1021atwr.h | 44 +++++++++++++++++++++++++++ 6 files changed, 95 insertions(+) create mode 100644 board/freescale/ls1021atwr/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021atwr_sdcard_defconfig diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 8def0e5ac4..2312e003cd 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -5,3 +5,4 @@ F: board/freescale/ls1021atwr/ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig +F: configs/ls1021atwr_sdcard_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 269d3e2c51..0faee0afad 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -18,6 +18,7 @@ #include #include #include +#include #ifdef CONFIG_U_QE #include "../../../drivers/qe/qe.h" #endif @@ -271,6 +272,25 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Set global data pointer */ + gd = &gdata; + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + board_init_r(NULL, 0); +} +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; diff --git a/board/freescale/ls1021atwr/ls102xa_pbi.cfg b/board/freescale/ls1021atwr/ls102xa_pbi.cfg new file mode 100644 index 0000000000..f1a1b63ab7 --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_pbi.cfg @@ -0,0 +1,12 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg new file mode 100644 index 0000000000..9c3e3b080b --- /dev/null +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg @@ -0,0 +1,14 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 + +#enable IFC, disable QSPI and DSPI +0608000a 00000000 00000000 00000000 +20000000 00407900 60040a00 21046000 +00000000 00000000 00000000 00038000 +00080000 881b7340 00000000 00000000 + +#disable IFC, enable QSPI and DSPI +#0608000a 00000000 00000000 00000000 +#20000000 00407900 60040a00 21046000 +#00000000 00000000 00000000 00038000 +#20084800 881b7340 00000000 00000000 diff --git a/configs/ls1021atwr_sdcard_defconfig b/configs/ls1021atwr_sdcard_defconfig new file mode 100644 index 0000000000..0eb556ad4c --- /dev/null +++ b/configs/ls1021atwr_sdcard_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b5ecde389a..9a5432278b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -35,6 +35,38 @@ #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -250,6 +282,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING + #define CONFIG_CMD_IMLS #define CONFIG_HWCONFIG @@ -295,7 +328,11 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif #define CONFIG_SYS_QE_FW_ADDR 0x67f40000 @@ -304,10 +341,17 @@ */ #define CONFIG_ENV_OVERWRITE +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x20000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP -- cgit v1.2.1 From 8251ed2323bf6594560a3c0a620f4742f8c024dc Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:37:34 +0800 Subject: arm: ls1021a: Add CONFIG_DOS_PARTITION and CONFIG_CMD_FAT support This patch will fix the bug that the partitions on the SD card could not be accessed and add the support for the FAT fs. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 3 +++ include/configs/ls1021atwr.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4a2e6098b9..df6843c64b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -312,6 +312,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * USB */ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 9a5432278b..aa9ec72fe6 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -212,6 +212,9 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + /* * Video */ -- cgit v1.2.1 From 4c59ab9cfbdd34f5ef1e960470accdc63e2483c1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:37:49 +0800 Subject: arm: ls102xa: Fix SD/NAND/QSPI boot defination error for QE support The SD/NAND/QSPI boot definations are wrong for QE support, this patch is to fix this error. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 3 ++- include/configs/ls1021atwr.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index df6843c64b..4496871ff3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -104,7 +104,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_FSL_CAAM /* Enable CAAM */ -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index aa9ec72fe6..972becd9a4 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -82,7 +82,8 @@ #define CONFIG_FSL_CAAM /* Enable CAAM */ -#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI) +#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ + !defined(CONFIG_QSPI_BOOT) #define CONFIG_U_QE #endif -- cgit v1.2.1 From d612f0ab34b27be4ad50b1236fbd6c84450997f1 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:02 +0800 Subject: arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 1 + board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 8 ++++++ board/freescale/ls1021atwr/MAINTAINERS | 1 + board/freescale/ls1021atwr/ls1021atwr.c | 14 ++++++++++ configs/ls1021aqds_qspi_defconfig | 3 ++ configs/ls1021atwr_qspi_defconfig | 3 ++ include/configs/ls1021aqds.h | 34 +++++++++++++++++++++++ include/configs/ls1021atwr.h | 28 +++++++++++++++++++ 9 files changed, 93 insertions(+) create mode 100644 configs/ls1021aqds_qspi_defconfig create mode 100644 configs/ls1021atwr_qspi_defconfig diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index b0c267cfc2..98b268dffe 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -98,6 +98,7 @@ struct ccsr_gur { #define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000 #define SCFG_PIXCLKCR_PXCKEN 0x80000000 +#define SCFG_QSPI_CLKSEL 0xc0100000 /* Supplemental Configuration Unit */ struct ccsr_scfg { diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 962176b533..7a704cf25f 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -7,3 +7,4 @@ F: configs/ls1021aqds_nor_defconfig F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_sdcard_defconfig +F: configs/ls1021aqds_qspi_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 9eab42d6c7..9fcd129883 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -34,7 +34,9 @@ enum { int checkboard(void) { +#ifndef CONFIG_QSPI_BOOT char buf[64]; +#endif #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT) u8 sw; #endif @@ -61,12 +63,14 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); #endif +#ifndef CONFIG_QSPI_BOOT printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", QIXIS_READ(id), QIXIS_READ(arch)); printf("FPGA: v%d (%s), build %d\n", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); +#endif return 0; } @@ -164,6 +168,10 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + /* Workaround for the issue that DDR could not respond to * barrier transaction which is generated by executing DSB/ISB * instruction. Set CCI-400 control override register to diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index 2312e003cd..91767065fa 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/ls1021atwr.h F: configs/ls1021atwr_nor_defconfig F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig F: configs/ls1021atwr_sdcard_defconfig +F: configs/ls1021atwr_qspi_defconfig diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0faee0afad..5c3a282b30 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -72,6 +72,7 @@ struct cpld_data { u8 rev2; /* Reserved */ }; +#ifndef CONFIG_QSPI_BOOT static void convert_serdes_mux(int type, int need_reset); void cpld_show(void) @@ -107,11 +108,14 @@ void cpld_show(void) in_8(&cpld_data->serdes_mux)); #endif } +#endif int checkboard(void) { puts("Board: LS1021ATWR\n"); +#ifndef CONFIG_QSPI_BOOT cpld_show(); +#endif return 0; } @@ -220,6 +224,7 @@ int board_eth_init(bd_t *bis) } #endif +#ifndef CONFIG_QSPI_BOOT int config_serdes_mux(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -251,6 +256,7 @@ int config_serdes_mux(void) return 0; } +#endif int board_early_init_f(void) { @@ -269,6 +275,10 @@ int board_early_init_f(void) out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); #endif +#ifdef CONFIG_FSL_QSPI + out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); +#endif + return 0; } @@ -305,8 +315,10 @@ int board_init(void) #ifndef CONFIG_SYS_FSL_NO_SERDES fsl_serdes_init(); +#ifndef CONFIG_QSPI_BOOT config_serdes_mux(); #endif +#endif #ifdef CONFIG_U_QE u_qe_init(); @@ -354,6 +366,7 @@ u16 flash_read16(void *addr) return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); } +#ifndef CONFIG_QSPI_BOOT static void convert_flash_bank(char bank) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); @@ -536,3 +549,4 @@ U_BOOT_CMD( " -change lane C & lane D to PCIeX2\n" "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" ); +#endif diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig new file mode 100644 index 0000000000..05ec8e6502 --- /dev/null +++ b/configs/ls1021aqds_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig new file mode 100644 index 0000000000..611f6e846a --- /dev/null +++ b/configs/ls1021atwr_qspi_defconfig @@ -0,0 +1,3 @@ +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4496871ff3..6f8b43f351 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -37,8 +37,14 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_QIXIS_I2C_ACCESS +#else #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() +#endif #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg @@ -73,6 +79,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -112,6 +123,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -204,6 +216,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif /* * QIXIS Definitions @@ -316,6 +329,18 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#endif + /* * USB */ @@ -394,7 +419,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -458,6 +487,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 972becd9a4..a3271fed05 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -67,6 +67,11 @@ #define CONFIG_SYS_MONITOR_LEN 0x80000 #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_TEXT_BASE 0x40010000 +#define CONFIG_SYS_NO_FLASH +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -90,6 +95,7 @@ /* * IFC Definitions */ +#ifndef CONFIG_QSPI_BOOT #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -133,6 +139,7 @@ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS #define CONFIG_SYS_WRITE_SWAPPED_DATA +#endif /* CPLD */ @@ -216,6 +223,18 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* QSPI */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_FSL_QSPI +#define QSPI0_AMBA_BASE 0x40000000 +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#endif + /* * Video */ @@ -287,7 +306,11 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_CMDLINE_EDITING +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_CMD_IMLS +#else #define CONFIG_CMD_IMLS +#endif #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 @@ -350,6 +373,11 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- cgit v1.2.1 From 8ab967b6c6007adbd30e58dfa9ef69154a351484 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 9 Dec 2014 17:38:14 +0800 Subject: arm: ls102xa: Add NAND boot support for LS1021AQDS board This patch adds NAND boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from NAND flash to DDR, finally SPL transfer control to u-boot. Signed-off-by: Prabhakar Kushwaha Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 2 + arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 5 ++ board/freescale/ls1021aqds/MAINTAINERS | 1 + board/freescale/ls1021aqds/ls1021aqds.c | 16 +++++ board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg | 7 +++ configs/ls1021aqds_nand_defconfig | 4 ++ drivers/mtd/nand/fsl_ifc_spl.c | 10 ++++ include/configs/ls1021aqds.h | 72 +++++++++++++++++++++++ 8 files changed, 117 insertions(+) create mode 100644 board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg create mode 100644 configs/ls1021aqds_nand_defconfig diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 704d683e83..ef775cf606 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -15,6 +15,8 @@ #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 +#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000) + #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 98b268dffe..5abc3a196e 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -29,6 +29,11 @@ #define ARCH_TIMER_CTRL_ENABLE (1 << 0) #define SYS_COUNTER_CTRL_ENABLE (1 << 24) +#define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000 +#define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000 + +#define DCFG_DCSR_PORCR1 0 + struct sys_info { unsigned long freq_processor[CONFIG_MAX_CPUS]; unsigned long freq_systembus; diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS index 7a704cf25f..638833dc41 100644 --- a/board/freescale/ls1021aqds/MAINTAINERS +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -8,3 +8,4 @@ F: configs/ls1021aqds_ddr4_nor_defconfig F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig F: configs/ls1021aqds_sdcard_defconfig F: configs/ls1021aqds_qspi_defconfig +F: configs/ls1021aqds_nand_defconfig diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 9fcd129883..691e828c02 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -187,6 +187,22 @@ void board_init_f(ulong dummy) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; +#ifdef CONFIG_NAND_BOOT + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 porsr1, pinctl; + + /* + * There is LS1 SoC issue where NOR, FPGA are inaccessible during + * NAND boot because IFC signals > IFC_AD7 are not enabled. + * This workaround changes RCW source to make all signals enabled. + */ + porsr1 = in_be32(&gur->porsr1); + pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) | + DCFG_CCSR_PORSR1_RCW_SRC_I2C); + out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + pinctl); +#endif + /* Set global data pointer */ gd = &gdata; diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg new file mode 100644 index 0000000000..222c71dcb6 --- /dev/null +++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol +0608000a 00000000 00000000 00000000 +60000000 00407900 e0106a00 21046000 +00000000 00000000 00000000 00038000 +00000000 001b7200 00000000 00000000 diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig new file mode 100644 index 0000000000..dad5274ae8 --- /dev/null +++ b/configs/ls1021aqds_nand_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_LS1021AQDS=y diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index e336cb1c94..fb827c5e74 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -254,3 +254,13 @@ void nand_boot(void) uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } + +#ifndef CONFIG_SPL_NAND_INIT +void nand_init(void) +{ +} + +void nand_deselect(void) +{ +} +#endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 6f8b43f351..536d9f3a58 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -84,6 +84,39 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NO_FLASH #endif +#ifdef CONFIG_NAND_BOOT +#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x10000000 +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 +#define CONFIG_SYS_TEXT_BASE 0x82000000 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif + #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x67f80000 #endif @@ -261,6 +294,40 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FPGA_FTIM3 0x0 #endif +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#else #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK @@ -293,6 +360,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 +#endif /* * Serial Port @@ -492,6 +560,10 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_NAND_BOOT) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -- cgit v1.2.1 From bca11bd7c31cb1f61dcbe727e0ff94c33c134b94 Mon Sep 17 00:00:00 2001 From: Yao Yuan Date: Wed, 26 Nov 2014 14:54:33 +0800 Subject: ls1021aqds: add hwconfig setting to do pin mux The Freescale LS1021AQDS share some pins, so Add the hwconfig option that allows the user to choose which the function he wants. The main pin mux IP is: eSDHC, SAI, IIC2, RGMII, CAN, SAI. Signed-off-by: Yuan Yao Reviewed-by: York Sun --- board/freescale/ls1021aqds/ls1021aqds.c | 73 +++++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 691e828c02..6c66bd42c3 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,9 +24,22 @@ #include "../../../drivers/qe/qe.h" #endif +#define PIN_MUX_SEL_CAN 0x03 +#define PIN_MUX_SEL_IIC2 0xa0 +#define PIN_MUX_SEL_RGMII 0x00 +#define PIN_MUX_SEL_SAI 0x0c +#define PIN_MUX_SEL_SDHC 0x00 + +#define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) +#define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) DECLARE_GLOBAL_DATA_PTR; enum { + MUX_TYPE_CAN, + MUX_TYPE_IIC2, + MUX_TYPE_RGMII, + MUX_TYPE_SAI, + MUX_TYPE_SDHC, MUX_TYPE_SD_PCI4, MUX_TYPE_SD_PC_SA_SG_SG, MUX_TYPE_SD_PC_SA_PC_SG, @@ -230,11 +244,27 @@ void board_init_f(ulong dummy) int config_board_mux(int ctrl_type) { - u8 reg12; + u8 reg12, reg14; reg12 = QIXIS_READ(brdcfg[12]); + reg14 = QIXIS_READ(brdcfg[14]); switch (ctrl_type) { + case MUX_TYPE_CAN: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_CAN); + break; + case MUX_TYPE_IIC2: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_IIC2); + break; + case MUX_TYPE_RGMII: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_RGMII); + break; + case MUX_TYPE_SAI: + reg14 = SET_EC_MUX_SEL(reg14, PIN_MUX_SEL_SAI); + break; + case MUX_TYPE_SDHC: + reg14 = SET_SDHC_MUX_SEL(reg14, PIN_MUX_SEL_SDHC); + break; case MUX_TYPE_SD_PCI4: reg12 = 0x38; break; @@ -253,6 +283,7 @@ int config_board_mux(int ctrl_type) } QIXIS_WRITE(brdcfg[12], reg12); + QIXIS_WRITE(brdcfg[14], reg14); return 0; } @@ -286,14 +317,50 @@ int config_serdes_mux(void) return 0; } -#if defined(CONFIG_MISC_INIT_R) int misc_init_r(void) { + int conflict_flag; + + /* some signals can not enable simultaneous*/ + conflict_flag = 0; + if (hwconfig("sdhc")) + conflict_flag++; + if (hwconfig("iic2")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + conflict_flag = 0; + if (hwconfig("rgmii")) + conflict_flag++; + if (hwconfig("can")) + conflict_flag++; + if (hwconfig("sai")) + conflict_flag++; + if (conflict_flag > 1) { + printf("WARNING: pin conflict !\n"); + return 0; + } + + if (hwconfig("can")) + config_board_mux(MUX_TYPE_CAN); + else if (hwconfig("rgmii")) + config_board_mux(MUX_TYPE_RGMII); + else if (hwconfig("sai")) + config_board_mux(MUX_TYPE_SAI); + + if (hwconfig("iic2")) + config_board_mux(MUX_TYPE_IIC2); + else if (hwconfig("sdhc")) + config_board_mux(MUX_TYPE_SDHC); + #ifdef CONFIG_FSL_CAAM return sec_init(); #endif + return 0; } -#endif int board_init(void) { -- cgit v1.2.1 From a1c04e2785fe9843abcaeaa5d46f819215550d90 Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Mon, 20 Oct 2014 16:50:49 +0530 Subject: drivers: usb: Make usb device-tree fixup code architecture independent move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/" so that it works independent of architecture it is running on Signed-off-by: Ramneek Mehresh Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- arch/powerpc/cpu/mpc8xxx/fdt.c | 104 ------------------------------------- drivers/usb/host/ehci-fsl.c | 113 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+), 104 deletions(-) diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index c6b4d95549..1c63f93f4d 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -73,110 +73,6 @@ void ft_fixup_num_cores(void *blob) { } #endif /* defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) */ -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, - const char *phy_type, int start_offset) -{ - const char *compat_dr = "fsl-usb2-dr"; - const char *compat_mph = "fsl-usb2-mph"; - const char *prop_mode = "dr_mode"; - const char *prop_type = "phy_type"; - const char *node_type = NULL; - int node_offset; - int err; - - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_mph); - if (node_offset < 0) { - node_offset = fdt_node_offset_by_compatible(blob, - start_offset, compat_dr); - if (node_offset < 0) { - printf("WARNING: could not find compatible" - " node %s or %s: %s.\n", compat_mph, - compat_dr, fdt_strerror(node_offset)); - return -1; - } else - node_type = compat_dr; - } else - node_type = compat_mph; - - if (mode) { - err = fdt_setprop(blob, node_offset, prop_mode, mode, - strlen(mode) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_mode, node_type, fdt_strerror(err)); - } - - if (phy_type) { - err = fdt_setprop(blob, node_offset, prop_type, phy_type, - strlen(phy_type) + 1); - if (err < 0) - printf("WARNING: could not set %s for %s: %s.\n", - prop_type, node_type, fdt_strerror(err)); - } - - return node_offset; -} - -void fdt_fixup_dr_usb(void *blob, bd_t *bd) -{ - const char *modes[] = { "host", "peripheral", "otg" }; - const char *phys[] = { "ulpi", "utmi" }; - int usb_mode_off = -1; - int usb_phy_off = -1; - char str[5]; - int i, j; - - for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { - const char *dr_mode_type = NULL; - const char *dr_phy_type = NULL; - int mode_idx = -1, phy_idx = -1; - snprintf(str, 5, "%s%d", "usb", i); - if (hwconfig(str)) { - for (j = 0; j < ARRAY_SIZE(modes); j++) { - if (hwconfig_subarg_cmp(str, "dr_mode", - modes[j])) { - mode_idx = j; - break; - } - } - - for (j = 0; j < ARRAY_SIZE(phys); j++) { - if (hwconfig_subarg_cmp(str, "phy_type", - phys[j])) { - phy_idx = j; - break; - } - } - - if (mode_idx < 0 && phy_idx < 0) { - printf("WARNING: invalid phy or mode\n"); - return; - } - - if (mode_idx > -1) - dr_mode_type = modes[mode_idx]; - - if (phy_idx > -1) - dr_phy_type = phys[phy_idx]; - } - - usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, - dr_mode_type, NULL, usb_mode_off); - - if (usb_mode_off < 0) - return; - - usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, - NULL, dr_phy_type, usb_phy_off); - - if (usb_phy_off < 0) - return; - } -} -#endif /* defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) */ - /* * update crypto node properties to a specified revision of the SEC * called with sec_rev == 0 if not on an E processor diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 8f554649e1..54efe5ef00 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -15,9 +15,14 @@ #include #include #include +#include #include "ehci.h" +#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + static void set_txfifothresh(struct usb_ehci *, u32); /* Check USB PHY clock valid */ @@ -158,3 +163,111 @@ static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) cmd |= TXFIFO_THRESH(txfifo_thresh); ehci_writel(&ehci->txfilltuning, cmd); } + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) +static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, + const char *phy_type, int start_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *prop_mode = "dr_mode"; + const char *prop_type = "phy_type"; + const char *node_type = NULL; + int node_offset; + int err; + + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, compat_mph); + if (node_offset < 0) { + node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (node_offset < 0) { + printf("WARNING: could not find compatible node: %s", + fdt_strerror(node_offset)); + return -1; + } + node_type = compat_dr; + } else { + node_type = compat_mph; + } + + if (mode) { + err = fdt_setprop(blob, node_offset, prop_mode, mode, + strlen(mode) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_mode, node_type, fdt_strerror(err)); + } + + if (phy_type) { + err = fdt_setprop(blob, node_offset, prop_type, phy_type, + strlen(phy_type) + 1); + if (err < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop_type, node_type, fdt_strerror(err)); + } + + return node_offset; +} + +void fdt_fixup_dr_usb(void *blob, bd_t *bd) +{ + static const char * const modes[] = { "host", "peripheral", "otg" }; + static const char * const phys[] = { "ulpi", "utmi" }; + int usb_mode_off = -1; + int usb_phy_off = -1; + char str[5]; + int i, j; + + for (i = 1; i <= CONFIG_USB_MAX_CONTROLLER_COUNT; i++) { + const char *dr_mode_type = NULL; + const char *dr_phy_type = NULL; + int mode_idx = -1, phy_idx = -1; + + snprintf(str, 5, "%s%d", "usb", i); + if (hwconfig(str)) { + for (j = 0; j < ARRAY_SIZE(modes); j++) { + if (hwconfig_subarg_cmp(str, "dr_mode", + modes[j])) { + mode_idx = j; + break; + } + } + + for (j = 0; j < ARRAY_SIZE(phys); j++) { + if (hwconfig_subarg_cmp(str, "phy_type", + phys[j])) { + phy_idx = j; + break; + } + } + + if (mode_idx < 0 && phy_idx < 0) { + printf("WARNING: invalid phy or mode\n"); + return; + } + + if (mode_idx > -1) + dr_mode_type = modes[mode_idx]; + + if (phy_idx > -1) + dr_phy_type = phys[phy_idx]; + } + + usb_mode_off = fdt_fixup_usb_mode_phy_type(blob, + dr_mode_type, NULL, + usb_mode_off); + + if (usb_mode_off < 0) + return; + + usb_phy_off = fdt_fixup_usb_mode_phy_type(blob, + NULL, dr_phy_type, + usb_phy_off); + + if (usb_phy_off < 0) + return; + } +} +#endif -- cgit v1.2.1 From ecfc19f31f1fa25f739d11c81d4810f9b35b29aa Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Tue, 30 Sep 2014 11:24:07 +0530 Subject: drivers: usb: fsl: Add USB device-tree errata framework Add a new framework for fsl usb erratum handling to standardize erratum checking only inside Uboot. Information to kernel is passed via a boolean property corresponding to erratum, hence eliminating need for code duplication inside kernel Signed-off-by: Ramneek Mehresh Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 64 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 54efe5ef00..61cd16840a 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -211,10 +211,57 @@ static int fdt_fixup_usb_mode_phy_type(void *blob, const char *mode, return node_offset; } +static const char *fdt_usb_get_node_type(void *blob, int start_offset, + int *node_offset) +{ + const char *compat_dr = "fsl-usb2-dr"; + const char *compat_mph = "fsl-usb2-mph"; + const char *node_type = NULL; + + *node_offset = fdt_node_offset_by_compatible(blob, start_offset, + compat_mph); + if (*node_offset < 0) { + *node_offset = fdt_node_offset_by_compatible(blob, + start_offset, + compat_dr); + if (*node_offset < 0) { + printf("ERROR: could not find compatible node: %s\n", + fdt_strerror(*node_offset)); + } else { + node_type = compat_dr; + } + } else { + node_type = compat_mph; + } + + return node_type; +} + +static int fdt_fixup_usb_erratum(void *blob, const char *prop_erratum, + int start_offset) +{ + int node_offset, err; + const char *node_type = NULL; + + node_type = fdt_usb_get_node_type(blob, start_offset, &node_offset); + if (!node_type) + return -1; + + err = fdt_setprop(blob, node_offset, prop_erratum, NULL, 0); + if (err < 0) { + printf("ERROR: could not set %s for %s: %s.\n", + prop_erratum, node_type, fdt_strerror(err)); + } + + return node_offset; +} + void fdt_fixup_dr_usb(void *blob, bd_t *bd) { static const char * const modes[] = { "host", "peripheral", "otg" }; static const char * const phys[] = { "ulpi", "utmi" }; + int usb_erratum_a006261_off = -1; + int usb_erratum_a007075_off = -1; int usb_mode_off = -1; int usb_phy_off = -1; char str[5]; @@ -268,6 +315,23 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) if (usb_phy_off < 0) return; + + if (has_erratum_a006261()) { + usb_erratum_a006261_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a006261", + usb_erratum_a006261_off); + if (usb_erratum_a006261_off < 0) + return; + } + if (has_erratum_a007075()) { + usb_erratum_a007075_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007075", + usb_erratum_a007075_off); + if (usb_erratum_a007075_off < 0) + return; + } } } #endif -- cgit v1.2.1 From da5ce448c731321ba8cad5502a35c669b5e1bf8c Mon Sep 17 00:00:00 2001 From: Nikhil Badola Date: Thu, 30 Oct 2014 10:11:28 +0530 Subject: drivers: usb: fsl: Check USB Erratum A007792 applicability Check USB Erratum A007792 applicability. If applicable, add corresponding property in the device tree via device tree fixup Signed-off-by: Nikhil Badola Reviewed-by: York Sun --- drivers/usb/host/ehci-fsl.c | 9 +++++++++ include/fsl_usb.h | 23 +++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 61cd16840a..5d4288d38f 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -262,6 +262,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) static const char * const phys[] = { "ulpi", "utmi" }; int usb_erratum_a006261_off = -1; int usb_erratum_a007075_off = -1; + int usb_erratum_a007792_off = -1; int usb_mode_off = -1; int usb_phy_off = -1; char str[5]; @@ -332,6 +333,14 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd) if (usb_erratum_a007075_off < 0) return; } + if (has_erratum_a007792()) { + usb_erratum_a007792_off = fdt_fixup_usb_erratum + (blob, + "fsl,usb-erratum-a007792", + usb_erratum_a007792_off); + if (usb_erratum_a007792_off < 0) + return; + } } } #endif diff --git a/include/fsl_usb.h b/include/fsl_usb.h index e4902aac96..d251f5d4ce 100644 --- a/include/fsl_usb.h +++ b/include/fsl_usb.h @@ -145,6 +145,25 @@ static inline bool has_erratum_a007798(void) return SVR_SOC_VER(get_svr()) == SVR_T4240 && IS_SVR_REV(get_svr(), 2, 0); } + +static inline bool has_erratum_a007792(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + switch (soc) { + case SVR_T4240: + case SVR_T4160: + return IS_SVR_REV(svr, 2, 0); + case SVR_T1040: + return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 1, 1); + } + return false; +} + #else static inline bool has_erratum_a006261(void) { @@ -161,5 +180,9 @@ static inline bool has_erratum_a007798(void) return false; } +static inline bool has_erratum_a007792(void) +{ + return false; +} #endif #endif /*_ASM_FSL_USB_H_ */ -- cgit v1.2.1 From a7787b78503a2c67fe02f1fcdd995fb6f3830f4b Mon Sep 17 00:00:00 2001 From: Tang Yuantian Date: Fri, 21 Nov 2014 11:17:15 +0800 Subject: fsl/sleep: updated the deep sleep framework for QorIQ platforms With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian Reviewed-by: York Sun --- board/freescale/common/Makefile | 6 +++ board/freescale/common/arm_sleep.c | 95 ++++++++++++++++++++++++++++++++++ board/freescale/common/mpc85xx_sleep.c | 88 +++++++++++++++++++++++++++++++ board/freescale/common/sleep.h | 21 ++++++++ drivers/ddr/fsl/arm_ddr_gen3.c | 45 +++++++++++++--- drivers/ddr/fsl/fsl_ddr_gen4.c | 44 ++++++++++++++-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 67 +++++++++--------------- include/fsl_ddr_sdram.h | 12 +++-- 8 files changed, 322 insertions(+), 56 deletions(-) create mode 100644 board/freescale/common/arm_sleep.c create mode 100644 board/freescale/common/mpc85xx_sleep.c create mode 100644 board/freescale/common/sleep.h diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 59ddeefcdc..9a91b9008a 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -37,6 +37,12 @@ endif obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o +ifdef CONFIG_ARM +obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o +else +obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o +endif + obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o obj-$(CONFIG_MPC8541CDS) += cds_pci_ft.o diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c new file mode 100644 index 0000000000..8edf8788ed --- /dev/null +++ b/board/freescale/common/arm_sleep.c @@ -0,0 +1,95 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#if !defined(CONFIG_ARMV7_NONSEC) || !defined(CONFIG_ARMV7_VIRT) +#error " Deep sleep needs non-secure mode support. " +#else +#include +#endif +#include +#include + +#if defined(CONFIG_LS102XA) +#include +#endif + +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + + if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_le32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache_all(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + board_sleep_prepare(); + armv7_init_nonsec(); + cleanup_before_linux(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_le32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + secure_ram_addr(_do_nonsec_entry)(kernel_resume, 0, 0, 0); + + return 0; +} diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c new file mode 100644 index 0000000000..f924e7f482 --- /dev/null +++ b/board/freescale/common/mpc85xx_sleep.c @@ -0,0 +1,88 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +void __weak board_mem_sleep_setup(void) +{ +} + +void __weak board_sleep_prepare(void) +{ +} + +bool is_warm_boot(void) +{ + struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) + return 1; + + return 0; +} + +void fsl_dp_disable_console(void) +{ + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; +} + +/* + * When wakeup from deep sleep, the first 128 bytes space + * will be used to do DDR training which corrupts the data + * in there. This function will restore them. + */ +static void dp_ddr_restore(void) +{ + volatile u64 *src, *dst; + int i; + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + /* get the address of ddr date from SPARECR3 */ + src = (u64 *)in_be32(&scfg->sparecr[2]); + dst = (u64 *)CONFIG_SYS_SDRAM_BASE; + + for (i = 0; i < DDR_BUFF_LEN / 8; i++) + *dst++ = *src++; + + flush_dcache(); +} + +static void dp_resume_prepare(void) +{ + dp_ddr_restore(); + + board_sleep_prepare(); + + l2cache_init(); +#if defined(CONFIG_RAMBOOT_PBL) + disable_cpc_sram(); +#endif + enable_cpc(); +} + +int fsl_dp_resume(void) +{ + u32 start_addr; + void (*kernel_resume)(void); + struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + + if (!is_warm_boot()) + return 0; + + dp_resume_prepare(); + + /* Get the entry address and jump to kernel */ + start_addr = in_be32(&scfg->sparecr[1]); + debug("Entry address is 0x%08x\n", start_addr); + kernel_resume = (void (*)(void))start_addr; + kernel_resume(); + + return 0; +} diff --git a/board/freescale/common/sleep.h b/board/freescale/common/sleep.h new file mode 100644 index 0000000000..c26c54264f --- /dev/null +++ b/board/freescale/common/sleep.h @@ -0,0 +1,21 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SLEEP_H +#define __SLEEP_H + +#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) +#define DDR_BUFF_LEN 128 + +/* determine if it is a wakeup from deep sleep */ +bool is_warm_boot(void); + +/* disable console output */ +void fsl_dp_disable_console(void); + +/* clean up everything and jump to kernel */ +int fsl_dp_resume(void); +#endif diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 59f2fd6610..c139da6da9 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -92,7 +92,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0); ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2); - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -105,9 +104,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); - ddr_out32(&ddr->init_addr, regs->ddr_init_addr); - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4); ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); @@ -128,7 +124,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } ddr_out32(&ddr->err_disable, regs->err_disable); ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -167,8 +180,20 @@ step2: udelay(500); asm volatile("dsb sy;isb"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; /* Let the controller go */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("dsb sy;isb"); @@ -211,4 +236,12 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif } diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index e024db9ee2..a3c01e7f1e 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -103,7 +103,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->dq_map_1, regs->dq_map_1); ddr_out32(&ddr->dq_map_2, regs->dq_map_2); ddr_out32(&ddr->dq_map_3, regs->dq_map_3); - ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3); ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode); ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); @@ -124,8 +123,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval); ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init); - ddr_out32(&ddr->init_addr, regs->ddr_init_addr); - ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); #ifndef CONFIG_SYS_FSL_DDR_EMU /* @@ -147,7 +144,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5); ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6); ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1); - ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + ddr_out32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + ddr_out32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + ddr_out32(&ddr->init_addr, regs->ddr_init_addr); + ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } ddr_out32(&ddr->err_disable, regs->err_disable); ddr_out32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -187,8 +201,20 @@ step2: mb(); isb(); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + /* do board specific memory setup */ + board_mem_sleep_setup(); + + temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; /* Let the controller go */ - temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI; ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); mb(); isb(); @@ -233,4 +259,12 @@ step2: if (timeout <= 0) printf("Waiting for D_INIT timeout. Memory may not work.\n"); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif } diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 4d5572ef21..8f4d01ad85 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -15,8 +15,6 @@ #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL #endif -DECLARE_GLOBAL_DATA_PTR; - /* * regs has the to-be-set values for DDR controller registers * ctrl_num is the DDR controller number @@ -44,16 +42,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, u32 save1, save2; #endif -#ifdef CONFIG_DEEP_SLEEP - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - bool sleep_flag = 0; -#endif - -#ifdef CONFIG_DEEP_SLEEP - if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - sleep_flag = 1; -#endif - switch (ctrl_num) { case 0: ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; @@ -130,13 +118,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) - out_be32(&ddr->sdram_cfg_2, - regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); - else -#endif - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3); @@ -149,17 +130,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); out_be32(&ddr->sdram_data_init, regs->ddr_data_init); out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { - out_be32(&ddr->init_addr, 0); - out_be32(&ddr->init_ext_addr, (1 << 31)); - } else -#endif - { - out_be32(&ddr->init_addr, regs->ddr_init_addr); - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); - } - out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4); out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); @@ -180,7 +150,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2); out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1); - out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); + out_be32(&ddr->init_addr, regs->ddr_init_addr); + out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); + out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2); + } out_be32(&ddr->err_disable, regs->err_disable); out_be32(&ddr->err_int_en, regs->err_int_en); for (i = 0; i < 32; i++) { @@ -400,21 +387,17 @@ step2: asm volatile("sync;isync"); #ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) { + if (is_warm_boot()) { /* enter self-refresh */ - setbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); /* do board specific memory setup */ board_mem_sleep_setup(); - } -#endif - - /* Let the controller go */ -#ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI); - else + } else #endif temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI); + + /* Let the controller go */ out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN); asm volatile("sync;isync"); @@ -566,8 +549,8 @@ step2: } #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */ #ifdef CONFIG_DEEP_SLEEP - if (sleep_flag) + if (is_warm_boot()) /* exit self-refresh */ - clrbits_be32(&ddr->sdram_cfg_2, (1 << 31)); + clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR); #endif } diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 5b03c14c55..095b33e29e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -114,6 +114,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_BI 0x00000001 +#define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG2_D_INIT 0x00000010 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 #define SDRAM_CFG2_ODT_NEVER 0 @@ -163,6 +164,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR1_ODT(x) ((x & DDR_CDR1_ODT_MASK) << DDR_CDR1_ODT_SHIFT) #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK) #define DDR_CDR2_VREF_OVRD(x) (0x00008080 | ((((x) - 37) & 0x3F) << 8)) +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) @@ -202,6 +204,8 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR_ODT_120ohm 0x6 #endif +#define DDR_INIT_ADDR_EXT_UIA (1 << 31) + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { @@ -414,9 +418,11 @@ static int __board_need_mem_reset(void) int board_need_mem_reset(void) __attribute__((weak, alias("__board_need_mem_reset"))); -void __weak board_mem_sleep_setup(void) -{ -} +#if defined(CONFIG_DEEP_SLEEP) +void board_mem_sleep_setup(void); +bool is_warm_boot(void); +int fsl_dp_resume(void); +#endif /* * The 85xx boards have a common prototype for fixed_sdram so put the -- cgit v1.2.1 From b8e5c7f94af6b178946ae01ba36ac7fac1e86ec7 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:54 +0800 Subject: ARM: HYP/non-sec: add the pen address BE mode support. For some SoCs, the pen address register maybe in BE mode and the CPUs are in LE mode. This patch adds BE mode support for smp pen address. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/nonsec_virt.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 745670e549..1ab5d54e30 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -191,6 +191,9 @@ ENTRY(smp_waitloop) wfi ldr r1, =CONFIG_SMP_PEN_ADDR @ load start address ldr r1, [r1] +#ifdef CONFIG_PEN_ADDR_BIG_ENDIAN + rev r1, r1 +#endif cmp r0, r1 @ make sure we dont execute this code beq smp_waitloop @ again (due to a spurious wakeup) mov r0, r1 -- cgit v1.2.1 From 73a1cb27c0d9e93d97cd7a344fd341f638ba3a2a Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:55 +0800 Subject: ARM: HYP/non-sec: Fix the ARCH Timer frequency setting. For some SoCs, the system clock frequency may not equal to the ARCH Timer's frequency. This patch uses the CONFIG_TIMER_CLK_FREQ instead of CONFIG_SYS_CLK_FREQ, then the system clock macro and arch timer macor could be set separately and without interfering each other. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/nonsec_virt.S | 4 ++-- include/configs/sun7i.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 1ab5d54e30..30d81db8b8 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -169,11 +169,11 @@ ENTRY(_nonsec_init) * we do this here instead. * But first check if we have the generic timer. */ -#ifdef CONFIG_SYS_CLK_FREQ +#ifdef CONFIG_TIMER_CLK_FREQ mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 and r0, r0, #CPUID_ARM_GENTIMER_MASK @ mask arch timer bits cmp r0, #(1 << CPUID_ARM_GENTIMER_SHIFT) - ldreq r1, =CONFIG_SYS_CLK_FREQ + ldreq r1, =CONFIG_TIMER_CLK_FREQ mcreq p15, 0, r1, c14, c0, 0 @ write CNTFRQ #endif diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index f6b1b3edc1..4426d24e57 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -25,6 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 +#define CONFIG_SYS_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * Include common sunxi configuration where most the settings are -- cgit v1.2.1 From 290e6e921f255fdee072d21539bbad16b9a3e714 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:56 +0800 Subject: ls1021a: adding a secondary core boot address and kick functions Define the board specific smp_set_cpu_boot_addr() function to set the start address for secondary cores in the LS1021A specific manner. Define the board specific smp_kick_all_cpus() functioin to boot a secondary core. Here the BRR contains control bits for enabling boot for each core. On exiting HRESET or PORESET, the RCW BOOT_HO field optionally allows for logical core 0 to be released for booting or to remain in boot holdoff. All other cores remain in boot holdoff until their corresponding bit is set. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index fae6c68efc..ce2d92f5a6 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -117,3 +117,21 @@ int arch_cpu_init(void) return 0; } + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT) +/* Set the address at which the secondary core starts from.*/ +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->scratchrw[0], addr); +} + +/* Release the secondary core from holdoff state and kick it */ +void smp_kick_all_cpus(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + out_be32(&gur->brrl, 0x2); +} +#endif -- cgit v1.2.1 From 1a2826f6e02d0d3ec97b77b5b13c13d2ac27fb9d Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:57 +0800 Subject: ls102xa: changing a few targets' configurations. Enable hypervisors utilizing the ARMv7 virtualization extension on the LS1021A-QDS/TWR boards with the A7 core tile, we add the required configuration variable. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 2 ++ arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +++ include/configs/ls1021aqds.h | 7 +++++++ include/configs/ls1021atwr.h | 7 +++++++ 4 files changed, 19 insertions(+) diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index ef775cf606..0533a83580 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -11,6 +11,8 @@ #define OCRAM_BASE_ADDR 0x10000000 #define OCRAM_SIZE 0x00020000 +#define OCRAM_BASE_S_ADDR 0x10010000 +#define OCRAM_S_SIZE 0x00010000 #define CONFIG_SYS_IMMR 0x01000000 #define CONFIG_SYS_DCSRBAR 0x20000000 diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 5abc3a196e..697d4ca489 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -17,6 +17,9 @@ #define SOC_VER_LS1021 0x11 #define SOC_VER_LS1022 0x12 +#define CCSR_BRR_OFFSET 0xe4 +#define CCSR_SCRATCHRW1_OFFSET 0x200 + #define RCWSR0_SYS_PLL_RAT_SHIFT 25 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f #define RCWSR0_MEM_PLL_RAT_SHIFT 16 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 536d9f3a58..704c349840 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -493,6 +493,13 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_IMLS #endif +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index a3271fed05..809e80f82c 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -312,6 +312,13 @@ #define CONFIG_CMD_IMLS #endif +#define CONFIG_ARMV7_NONSEC +#define CONFIG_ARMV7_VIRT +#define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define CONFIG_TIMER_CLK_FREQ 12500000 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 -- cgit v1.2.1 From e87f3b308c454f6e78b02da857936c7d012c385b Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:58 +0800 Subject: ARM: ls102xa: allow all the peripheral access permission as R/W. The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 1 + arch/arm/include/asm/arch-ls102xa/ns_access.h | 118 ++++++++++++++++++++++++++ board/freescale/common/Makefile | 2 + board/freescale/common/ns_access.c | 30 +++++++ board/freescale/ls1021aqds/ls1021aqds.c | 91 ++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 91 ++++++++++++++++++++ include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + 8 files changed, 335 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/ns_access.h create mode 100644 board/freescale/common/ns_access.c diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 0533a83580..5e934da797 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -21,6 +21,7 @@ #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x00180000) +#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) diff --git a/arch/arm/include/asm/arch-ls102xa/ns_access.h b/arch/arm/include/asm/arch-ls102xa/ns_access.h new file mode 100644 index 0000000000..b53f69951a --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ns_access.h @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_NS_ACCESS_H_ +#define __FSL_NS_ACCESS_H_ + +enum csu_cslx_access { + CSU_NS_SUP_R = 0x08, + CSU_NS_SUP_W = 0x80, + CSU_NS_SUP_RW = 0x88, + CSU_NS_USER_R = 0x04, + CSU_NS_USER_W = 0x40, + CSU_NS_USER_RW = 0x44, + CSU_S_SUP_R = 0x02, + CSU_S_SUP_W = 0x20, + CSU_S_SUP_RW = 0x22, + CSU_S_USER_R = 0x01, + CSU_S_USER_W = 0x10, + CSU_S_USER_RW = 0x11, + CSU_ALL_RW = 0xff, +}; + +enum csu_cslx_ind { + CSU_CSLX_PCIE2_IO = 0, + CSU_CSLX_PCIE1_IO, + CSU_CSLX_MG2TPR_IP, + CSU_CSLX_IFC_MEM, + CSU_CSLX_OCRAM, + CSU_CSLX_GIC, + CSU_CSLX_PCIE1, + CSU_CSLX_OCRAM2, + CSU_CSLX_QSPI_MEM, + CSU_CSLX_PCIE2, + CSU_CSLX_SATA, + CSU_CSLX_USB3, + CSU_CSLX_SERDES = 32, + CSU_CSLX_QDMA, + CSU_CSLX_LPUART2, + CSU_CSLX_LPUART1, + CSU_CSLX_LPUART4, + CSU_CSLX_LPUART3, + CSU_CSLX_LPUART6, + CSU_CSLX_LPUART5, + CSU_CSLX_DSPI2 = 40, + CSU_CSLX_DSPI1, + CSU_CSLX_QSPI, + CSU_CSLX_ESDHC, + CSU_CSLX_2D_ACE, + CSU_CSLX_IFC, + CSU_CSLX_I2C1, + CSU_CSLX_USB2, + CSU_CSLX_I2C3, + CSU_CSLX_I2C2, + CSU_CSLX_DUART2 = 50, + CSU_CSLX_DUART1, + CSU_CSLX_WDT2, + CSU_CSLX_WDT1, + CSU_CSLX_EDMA, + CSU_CSLX_SYS_CNT, + CSU_CSLX_DMA_MUX2, + CSU_CSLX_DMA_MUX1, + CSU_CSLX_DDR, + CSU_CSLX_QUICC, + CSU_CSLX_DCFG_CCU_RCPM = 60, + CSU_CSLX_SECURE_BOOTROM, + CSU_CSLX_SFP, + CSU_CSLX_TMU, + CSU_CSLX_SECURE_MONITOR, + CSU_CSLX_RESERVED0, + CSU_CSLX_ETSEC1, + CSU_CSLX_SEC5_5, + CSU_CSLX_ETSEC3, + CSU_CSLX_ETSEC2, + CSU_CSLX_GPIO2 = 70, + CSU_CSLX_GPIO1, + CSU_CSLX_GPIO4, + CSU_CSLX_GPIO3, + CSU_CSLX_PLATFORM_CONT, + CSU_CSLX_CSU, + CSU_CSLX_ASRC, + CSU_CSLX_SPDIF, + CSU_CSLX_FLEXCAN2, + CSU_CSLX_FLEXCAN1, + CSU_CSLX_FLEXCAN4 = 80, + CSU_CSLX_FLEXCAN3, + CSU_CSLX_SAI2, + CSU_CSLX_SAI1, + CSU_CSLX_SAI4, + CSU_CSLX_SAI3, + CSU_CSLX_FTM2, + CSU_CSLX_FTM1, + CSU_CSLX_FTM4, + CSU_CSLX_FTM3, + CSU_CSLX_FTM6 = 90, + CSU_CSLX_FTM5, + CSU_CSLX_FTM8, + CSU_CSLX_FTM7, + CSU_CSLX_COP_DCSR, + CSU_CSLX_EPU, + CSU_CSLX_GDI, + CSU_CSLX_DDI, + CSU_CSLX_RESERVED1, + CSU_CSLX_USB3_PHY = 117, + CSU_CSLX_RESERVED2, + CSU_CSLX_MAX, +}; + +struct csu_ns_dev { + unsigned long ind; + uint32_t val; +}; + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num); + +#endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 9a91b9008a..148fc41102 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -68,4 +68,6 @@ obj-$(CONFIG_P3041DS) += p_corenet/ obj-$(CONFIG_P4080DS) += p_corenet/ obj-$(CONFIG_P5020DS) += p_corenet/ obj-$(CONFIG_P5040DS) += p_corenet/ + +obj-$(CONFIG_LS102XA_NS_ACCESS) += ns_access.o endif diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c new file mode 100644 index 0000000000..d7de9822d0 --- /dev/null +++ b/board/freescale/common/ns_access.c @@ -0,0 +1,30 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num) +{ + u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; + u32 *reg; + uint32_t val; + int i; + + for (i = 0; i < num; i++) { + reg = base + ns_dev[i].ind / 2; + val = in_be32(reg); + if (ns_dev[i].ind % 2 == 0) { + val &= 0x0000ffff; + val |= ns_dev[i].val << 16; + } else { + val &= 0xffff0000; + val |= ns_dev[i].val; + } + out_be32(reg, val); + } +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 6c66bd42c3..1679144caa 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -362,6 +363,92 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -384,6 +471,10 @@ int board_init(void) config_serdes_mux(); #endif +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 5c3a282b30..0e61abaa76 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -301,6 +302,92 @@ void board_init_f(ulong dummy) } #endif +#ifdef CONFIG_LS102XA_NS_ACCESS +static struct csu_ns_dev ns_dev[] = { + { CSU_CSLX_PCIE2_IO, CSU_ALL_RW }, + { CSU_CSLX_PCIE1_IO, CSU_ALL_RW }, + { CSU_CSLX_MG2TPR_IP, CSU_ALL_RW }, + { CSU_CSLX_IFC_MEM, CSU_ALL_RW }, + { CSU_CSLX_OCRAM, CSU_ALL_RW }, + { CSU_CSLX_GIC, CSU_ALL_RW }, + { CSU_CSLX_PCIE1, CSU_ALL_RW }, + { CSU_CSLX_OCRAM2, CSU_ALL_RW }, + { CSU_CSLX_QSPI_MEM, CSU_ALL_RW }, + { CSU_CSLX_PCIE2, CSU_ALL_RW }, + { CSU_CSLX_SATA, CSU_ALL_RW }, + { CSU_CSLX_USB3, CSU_ALL_RW }, + { CSU_CSLX_SERDES, CSU_ALL_RW }, + { CSU_CSLX_QDMA, CSU_ALL_RW }, + { CSU_CSLX_LPUART2, CSU_ALL_RW }, + { CSU_CSLX_LPUART1, CSU_ALL_RW }, + { CSU_CSLX_LPUART4, CSU_ALL_RW }, + { CSU_CSLX_LPUART3, CSU_ALL_RW }, + { CSU_CSLX_LPUART6, CSU_ALL_RW }, + { CSU_CSLX_LPUART5, CSU_ALL_RW }, + { CSU_CSLX_DSPI2, CSU_ALL_RW }, + { CSU_CSLX_DSPI1, CSU_ALL_RW }, + { CSU_CSLX_QSPI, CSU_ALL_RW }, + { CSU_CSLX_ESDHC, CSU_ALL_RW }, + { CSU_CSLX_2D_ACE, CSU_ALL_RW }, + { CSU_CSLX_IFC, CSU_ALL_RW }, + { CSU_CSLX_I2C1, CSU_ALL_RW }, + { CSU_CSLX_USB2, CSU_ALL_RW }, + { CSU_CSLX_I2C3, CSU_ALL_RW }, + { CSU_CSLX_I2C2, CSU_ALL_RW }, + { CSU_CSLX_DUART2, CSU_ALL_RW }, + { CSU_CSLX_DUART1, CSU_ALL_RW }, + { CSU_CSLX_WDT2, CSU_ALL_RW }, + { CSU_CSLX_WDT1, CSU_ALL_RW }, + { CSU_CSLX_EDMA, CSU_ALL_RW }, + { CSU_CSLX_SYS_CNT, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX2, CSU_ALL_RW }, + { CSU_CSLX_DMA_MUX1, CSU_ALL_RW }, + { CSU_CSLX_DDR, CSU_ALL_RW }, + { CSU_CSLX_QUICC, CSU_ALL_RW }, + { CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW }, + { CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW }, + { CSU_CSLX_SFP, CSU_ALL_RW }, + { CSU_CSLX_TMU, CSU_ALL_RW }, + { CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW }, + { CSU_CSLX_RESERVED0, CSU_ALL_RW }, + { CSU_CSLX_ETSEC1, CSU_ALL_RW }, + { CSU_CSLX_SEC5_5, CSU_ALL_RW }, + { CSU_CSLX_ETSEC3, CSU_ALL_RW }, + { CSU_CSLX_ETSEC2, CSU_ALL_RW }, + { CSU_CSLX_GPIO2, CSU_ALL_RW }, + { CSU_CSLX_GPIO1, CSU_ALL_RW }, + { CSU_CSLX_GPIO4, CSU_ALL_RW }, + { CSU_CSLX_GPIO3, CSU_ALL_RW }, + { CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW }, + { CSU_CSLX_CSU, CSU_ALL_RW }, + { CSU_CSLX_ASRC, CSU_ALL_RW }, + { CSU_CSLX_SPDIF, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN2, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN1, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN4, CSU_ALL_RW }, + { CSU_CSLX_FLEXCAN3, CSU_ALL_RW }, + { CSU_CSLX_SAI2, CSU_ALL_RW }, + { CSU_CSLX_SAI1, CSU_ALL_RW }, + { CSU_CSLX_SAI4, CSU_ALL_RW }, + { CSU_CSLX_SAI3, CSU_ALL_RW }, + { CSU_CSLX_FTM2, CSU_ALL_RW }, + { CSU_CSLX_FTM1, CSU_ALL_RW }, + { CSU_CSLX_FTM4, CSU_ALL_RW }, + { CSU_CSLX_FTM3, CSU_ALL_RW }, + { CSU_CSLX_FTM6, CSU_ALL_RW }, + { CSU_CSLX_FTM5, CSU_ALL_RW }, + { CSU_CSLX_FTM8, CSU_ALL_RW }, + { CSU_CSLX_FTM7, CSU_ALL_RW }, + { CSU_CSLX_COP_DCSR, CSU_ALL_RW }, + { CSU_CSLX_EPU, CSU_ALL_RW }, + { CSU_CSLX_GDI, CSU_ALL_RW }, + { CSU_CSLX_DDI, CSU_ALL_RW }, + { CSU_CSLX_RESERVED1, CSU_ALL_RW }, + { CSU_CSLX_USB3_PHY, CSU_ALL_RW }, + { CSU_CSLX_RESERVED2, CSU_ALL_RW }, +}; +#endif + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -320,6 +407,10 @@ int board_init(void) #endif #endif +#ifdef CONFIG_LS102XA_NS_ACCESS + enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); +#endif + #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 704c349840..73918825a5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -496,6 +496,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 809e80f82c..171346b8e1 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -315,6 +315,7 @@ #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN +#define CONFIG_LS102XA_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 #define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR -- cgit v1.2.1 From 660673af4fd10c544ceeedeb524ba92c27dbc586 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Fri, 21 Nov 2014 17:40:59 +0800 Subject: ARM: ls102xa: Setting device's stream id for SMMUs. LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li Reviewed-by: York Sun --- .../include/asm/arch-ls102xa/ls102xa_stream_id.h | 17 +++++++++++++++++ board/freescale/common/Makefile | 2 ++ board/freescale/common/ls102xa_stream_id.c | 18 ++++++++++++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 21 +++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 21 +++++++++++++++++++++ include/configs/ls1021aqds.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ 7 files changed, 83 insertions(+) create mode 100644 arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h create mode 100644 board/freescale/common/ls102xa_stream_id.c diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h new file mode 100644 index 0000000000..abd70fc706 --- /dev/null +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_LS102XA_STREAM_ID_H_ +#define __FSL_LS102XA_STREAM_ID_H_ + +struct smmu_stream_id { + uint16_t offset; + uint16_t stream_id; + char dev_name[32]; +}; + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num); +#endif diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 148fc41102..14af660087 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -62,6 +62,8 @@ obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o +obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o + # deal with common files for P-series corenet based devices obj-$(CONFIG_P2041RDB) += p_corenet/ obj-$(CONFIG_P3041DS) += p_corenet/ diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c new file mode 100644 index 0000000000..6154c9c458 --- /dev/null +++ b/board/freescale/common/ls102xa_stream_id.c @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) +{ + uint32_t *scfg = (uint32_t *)CONFIG_SYS_FSL_SCFG_ADDR; + int i; + + for (i = 0; i < num; i++) + out_be32(scfg + id[i].offset, id[i].stream_id); +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 1679144caa..f08e54f178 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -449,6 +450,23 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -471,6 +489,9 @@ int board_init(void) config_serdes_mux(); #endif + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 0e61abaa76..8ab229ddf0 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -388,6 +389,23 @@ static struct csu_ns_dev ns_dev[] = { }; #endif +struct smmu_stream_id dev_stream_id[] = { + { 0x100, 0x01, "ETSEC MAC1" }, + { 0x104, 0x02, "ETSEC MAC2" }, + { 0x108, 0x03, "ETSEC MAC3" }, + { 0x10c, 0x04, "PEX1" }, + { 0x110, 0x05, "PEX2" }, + { 0x114, 0x06, "qDMA" }, + { 0x118, 0x07, "SATA" }, + { 0x11c, 0x08, "USB3" }, + { 0x120, 0x09, "QE" }, + { 0x124, 0x0a, "eSDHC" }, + { 0x128, 0x0b, "eMA" }, + { 0x14c, 0x0c, "2D-ACE" }, + { 0x150, 0x0d, "USB2" }, + { 0x18c, 0x0e, "DEBUG" }, +}; + int board_init(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -407,6 +425,9 @@ int board_init(void) #endif #endif + ls102xa_config_smmu_stream_id(dev_stream_id, + ARRAY_SIZE(dev_stream_id)); + #ifdef CONFIG_LS102XA_NS_ACCESS enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev)); #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 73918825a5..8dc04f2e57 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -536,6 +536,8 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 171346b8e1..66954d0a40 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -352,6 +352,8 @@ #define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_LS102XA_STREAM_ID + /* * Stack sizes * The stack sizes are set up in start.S using the settings below -- cgit v1.2.1 From 1d421cc6773dd9090e8b9202a24038561a28e56c Mon Sep 17 00:00:00 2001 From: Jaiprakash Singh Date: Thu, 27 Nov 2014 12:38:12 +0530 Subject: driver/mtd: Fix IFC compilation warnings 'eccstat' array elements might be used uninitialized Signed-off-by: Jaiprakash Singh Reviewed-by: York Sun --- drivers/mtd/nand/fsl_ifc_nand.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index 81b5070b54..b283eaea34 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -292,7 +292,7 @@ static int fsl_ifc_run_command(struct mtd_info *mtd) struct fsl_ifc *ifc = ctrl->regs; u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; u32 time_start; - u32 eccstat[4]; + u32 eccstat[4] = {0}; int i; /* set the chip select for NAND Transaction */ -- cgit v1.2.1 From 0de15707a71ec64dbc1ead2831457f1550179ea7 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Wed, 3 Dec 2014 16:18:09 +0800 Subject: kconfig: ls102xa: Change the prompt messages As NOR/NAND/SD boot are all supported on LS1021AQDS/TWR boards, the prompt message "Support ls1021aqds_nor" in Kconfig is not clear. This patch changes it to "Support ls1021aqds". Signed-off-by: Alison Wang Reviewed-by: York Sun --- arch/arm/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 11ae5f8b6c..c026dec0ac 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -728,12 +728,12 @@ config TARGET_LS2085A_SIMU select ARM64 config TARGET_LS1021AQDS - bool "Support ls1021aqds_nor" + bool "Support ls1021aqds" select CPU_V7 select SUPPORT_SPL config TARGET_LS1021ATWR - bool "Support ls1021atwr_nor" + bool "Support ls1021atwr" select CPU_V7 select SUPPORT_SPL -- cgit v1.2.1 From d0419f400af6f4bbe5c4ee5c97f6fbbdedec6cf3 Mon Sep 17 00:00:00 2001 From: Xiubo Li Date: Thu, 11 Dec 2014 11:15:26 -0800 Subject: ARM: HYP/non-sec: Fix the ARCH Timer frequency setting for sun7i Earlier commit 73a1cb27 mistakenly used CONFIG_SYS_TIMER_CLK_FREQ. It should be CONFIG_TIMER_CLK_FREQ. Signed-off-by: Xiubo Li [York Sun: This is the difference between two patch versions] Reviewed-by: York Sun --- include/configs/sun7i.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 4426d24e57..ccec50c328 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -25,7 +25,7 @@ #define CONFIG_ARMV7_PSCI 1 #define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE #define CONFIG_SYS_CLK_FREQ 24000000 -#define CONFIG_SYS_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ +#define CONFIG_TIMER_CLK_FREQ CONFIG_SYS_CLK_FREQ /* * Include common sunxi configuration where most the settings are -- cgit v1.2.1