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* armv8/ls2085a_emu: Enable sync of refreshYork Sun2015-02-241-0/+1
| | | | | | | Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun <yorksun@freescale.com>
* ls2085/configs: Ensure right banners are printed for EMU and SIMUBhupesh Sharma2015-02-241-0/+3
| | | | | | | | This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-251-0/+1
| | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
* ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board supportYork Sun2014-07-041-0/+19
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
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