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* x86: Rename coreboot-serial to x86-serialBin Meng2014-12-181-1/+1
| | | | | Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SDHCI supportBin Meng2014-12-181-0/+6
| | | | | | | | | There are two standard SD card slots on the Crown Bay board, which are connected to the Topcliff PCH SDIO controllers. Enable the SDHC support so that we can use them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable Intel E1000 NIC supportBin Meng2014-12-181-0/+1
| | | | | | | | | We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add SPI flash supportBin Meng2014-12-181-0/+2
| | | | | | | | | The Crown Bay board has an SST25VF016B flash connected to the Tunnel Creek processor SPI controller used as the BIOS media where U-Boot is stored. Enable this flash support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add crownbay defconfig and config.hBin Meng2014-12-181-0/+52
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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