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* sf: Move SPI flash drivers to defconfigBin Meng2015-11-251-1/+0
| | | | | | | | There are already Kconfig options for SPI flash drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* spi: Move SPI drivers to defconfigBin Meng2015-11-251-1/+0
| | | | | | | | There are already Kconfig options for SPI drivers, but we have not moved them from config.h to defconfig files. This commit does this in a batch. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* ns16550: move CONFIG_SYS_NS16550 to KconfigThomas Chou2015-11-211-1/+0
| | | | | | Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* arm, powerpc: select SYS_GENERIC_BOARDMasahiro Yamada2015-10-241-1/+0
| | | | | | | | | | | We have finished Generic Board conversion for ARM and PowerPC, i.e. all the boards have been converted except OpenRISC, SuperH, SPARC, which have not supported Generic Board framework yet. Select SYS_GENERIC_BOARD in arch/Kconfig and delete all the macro defines in include/configs/*.h. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* cmd: Convert CONFIG_CMD_ELF to KconfigBin Meng2015-10-211-1/+0
| | | | | | Convert CONFIG_CMD_ELF to Kconfig and tidy up affected boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* powerpc: configs: Fix init_ram physical address for several boardsYork Sun2015-09-011-2/+2
| | | | | | | | For e6500 and e5500 SoCs, it was intended to put init_ram address in ccsr reserved space. It is no longer true since SerDes module took the space. Move it to another reserved space at CCSR + 0x03c000. Signed-off-by: York Sun <yorksun@freescale.com>
* net: Move CONFIG_E1000 options to KconfigSimon Glass2015-08-211-1/+0
| | | | | | | | Move config for the E1000 Ethernet driver to Kconfig and tidy up affected boards. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* configs: Remove CONFIG_SERIAL_MULTIStephen Warren2015-08-051-1/+0
| | | | | | | This config option isn't used anywhere at all. Remove all places that define/enable the option. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* Move defaults from config_cmd_default.h to KconfigJoe Hershberger2015-06-251-2/+0
| | | | | | | | | | This sets the default commands Kconfig to match include/config_cmd_default.h commands in the common/Kconfig and removes them from include/configs. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates] Signed-off-by: Tom Rini <trini@konsulko.com>
* Move default y configs out of arch/board KconfigJoe Hershberger2015-06-251-1/+0
| | | | | | | | | | | | | | | | | | | Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate. Remove the configs that behave this way from the archs. A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be: SPIFLASH DISPLAY_BOARDINFO Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: remove CONFIG_NET_MULTILars Poeschel2015-06-021-1/+0
| | | | | | | | | CONFIG_NET_MULTI is not used anywhere and thus can safely be removed from the configs. Acked-by: Marek Vasut <marex@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
* net: Move the CMD_NET config to defconfigsJoe Hershberger2015-06-011-1/+0
| | | | | | | | | | | This also selects CONFIG_NET for any CONFIG_CMD_NET board. Remove the imx default for CONFIG_NET. This moves the config that was defined by 60296a8 (commands: add more command entries in Kconfig). Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
* Move setexpr to KconfigJoe Hershberger2015-06-011-1/+0
| | | | | | | | | | | Another shell scripting command that has not been moved. Moved using tools/moveconfig.py using these settings: CMD_SETEXPR bool n y Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
* nand: Remove CONFIG_MTD_NAND_VERIFY_WRITEPeter Tyser2015-03-301-1/+0
| | | | | | | | | The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mpc85xx: inhibit qman and bman portals by defaultJeffrey Ladouceur2014-12-151-0/+16
| | | | | | | | | Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/b4860qds: add workaround for XFIShaohui Xie2014-12-051-0/+2
| | | | | | | | | | | | | | | XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* B4860QDS: SGMII related updatesShaveta Leekha2014-12-051-2/+2
| | | | | | | | | | | | | | - Enable SGMII support for 0x8d Serdes 2 protocol. - Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol. - Updated debug statement - Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1) - Rename onboard PHY address defines for more readability - Add these new Defines in B4860QDS.h file Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs - Enable blob command in freescale platformsRuchika Gupta2014-10-161-0/+4
| | | | | | | | Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs - Add hash command in freescale platformsRuchika Gupta2014-10-161-0/+7
| | | | | | | | | Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* B4860QDS: Enable mac command supportShaveta Leekha2014-09-241-0/+1
| | | | | | | | One of the I2C EEPROM is used to store/save and edit mac addresses of ports. this patch add required CONFIG to support the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
* powerpc/b4860: Updated default hwconfig to enable only cpc2Shaveta Leekha2014-09-241-2/+9
| | | | | | | | | | CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* include: remove CONFIG_SPL/CONFIG_TPL definition in config headersMasahiro Yamada2014-07-301-1/+0
| | | | | | | | | Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig. Remove the redundant definition in config headers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* include: define CONFIG_SPL and CONFIG_TPL as 1Masahiro Yamada2014-07-301-1/+1
| | | | | | | | | | | | | | | | We are about to switch to Kconfig in the next commit. But there are something to get done beforehand. In Kconfig, include/generated/autoconf.h defines boolean CONFIG macros as 1. CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1. Otherwise, when switching to Kconfig, the build log would be sprinkled with warning messages like this: warning: "CONFIG_SPL" redefined [enabled by default] Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* powerpc/ifc: fix invalid CSn FTIM2.TCH settingShaohui Xie2014-07-221-1/+1
| | | | | | | | | On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE bootLiu Gang2014-05-161-5/+5
| | | | | | | | | | | | | | | | | The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations. The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mpc85xx: configs: remove c=ffe from default environmentKim Phillips2014-05-161-2/+1
| | | | | | | | | | | AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Edward Swarthout <ed.swarthout@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/freescale: Convert selected boards to generic board architectureYork Sun2014-05-131-0/+3
| | | | | | | | | | | | | | This patch converts the following boards to use generic board: MPC8536DS, MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS, P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS. Signed-off-by: York Sun <yorksun@freescale.com> CC: Ying Zhang <b40530@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Haijun.Zhang <Haijun.Zhang@freescale.com> CC: Scott Wood <scottwood@freescale.com> CC: Shaohui Xie <Shaohui.Xie@freescale.com>
* board/b4qds: VID supportShaveta Leekha2014-05-131-0/+11
| | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* powerpc/mpc85xx:Update MONITOR_LEN for 768KB u-boot sizePrabhakar Kushwaha2014-04-221-1/+1
| | | | | | | | | U-boot binary size has been increased from 512KB to 768KB. So update CONFIG_SYS_MONITOR_LEN to reflect the same. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/b4qds:Add support of 2 stage NAND boot-loaderPrabhakar Kushwaha2014-04-221-7/+57
| | | | | | | | | | | | | | Add support of 2 stage NAND boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot. Initialise/create followings required for SPL framework - Add spl.c which defines board_init_f, board_init_r - update tlb and ddr accordingly Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* QE/FMAN: modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and ↵Zhao Qiang2014-04-221-5/+5
| | | | | | | | | | | CONFIG_SYS_QE_FW_ADDR CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address. Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address, and CONFIG_SYS_QE_FW_ADDR for QE microcode address. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: pblimage: refactor CONFIG_SYS_FSL_PBL_{PBI, RCW}Masahiro Yamada2014-03-121-2/+2
| | | | | | | | | | Pull out "$(SRCTREE)/" from CONFIG_SYS_FSL_PBL_PBI and CONFIG_SYS_FSL_PBL_RCW and push it into the top Makefile. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com> Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
* powerpc: mpc85xx: move CONFIG_MPC85xx definition to CPU config.mkMasahiro Yamada2014-01-241-1/+0
| | | | | | | Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk because all target boards with mpc85xx cpu define it. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* powerpc/mpc85xx:Increase binary size for P, B & T series boards.Prabhakar Kushwaha2014-01-211-4/+4
| | | | | | | | | | | u-boot binary size for Freescale mpc85xx platforms is 512KB. This has been reached to upper limit for some of the platforms causig linker error. So, Increase the u-boot binary size to 768KB. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* powerpc:Rename CONFIG_PBLRCW_CONFIG & CONFIG_SYS_FSL_PBL_PBIPrabhakar Kushwaha2014-01-211-2/+2
| | | | | | | | | Rename CONFIG_PBLRCW_CONFIG and CONFIG_PBLRCW_CONFIG. Also add their details in README. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/B4860QDS: Define new nand_ecclayout structure macrosYork Sun2014-01-021-0/+2
| | | | | | | | | | Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to reduce the image size, by taking advantage of the new nand_ecclayout structure. Signed-off-by: York Sun <yorksun@freescale.com> CC: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Scott Wood <scottwood@freescale.com>
* kgdb: configs: remove obsolete CONFIG_KGDB_SER_INDEXVladimir Zapolskiy2013-12-131-1/+0
| | | | | | | | The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years ago in commits 550650ddd0 and bf16500f79, either kgdb subsystem should care about this parameter or it should be gone completely. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-251-1/+1
| | | | | | | Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
* config: remove platform CONFIG_SYS_HZ definition part 1/2Rob Herring2013-11-041-1/+0
| | | | | | Remove platform CONFIG_SYS_HZ definition for configs A-Z*. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* config: Add a default CONFIG_SYS_PROMPTRob Herring2013-11-041-1/+0
| | | | | | | | | | The definitions for CONFIG_SYS_PROMPT are varied with little reason other than to display the board name. Over half the definitions are "==> ", so make this the default. The rest of the boards remain unchanged to avoid breaking any external scripts expecting a certain prompt. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* powerpc/B4860: enable PBL tool for B4860Shaohui Xie2013-10-161-0/+2
| | | | | | | | Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu2013-10-161-2/+0
| | | | | | | This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
* powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-091-0/+2
| | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* board/b4860qds: Add support for configuring SerDes1 RefclksShaveta Leekha2013-08-091-0/+7
| | | | | | | | | | | | | | | | | | 1) Add support in B4860 board files for using IDT driver where IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer that generate different refclks for SerDes modules, used this driver for reconfiguring SerDes1 Refclks(based on SerDes1 protocols) for CPRI to work. CPRI works on 122.88MHz and default refclks coming on board are not suitable for it 2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file to b4860qds board file, as SerDes1 Refclk1 would come from PHY MUX in case of certain protocols, that have been checked here. This change would make on board SGMIIs to work 3) Add I2C addresses for IDT8T49N222A devices in board/include file 4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/corenet: Move CONFIG_FSL_CORENET out of board header fileYork Sun2013-08-091-1/+0
| | | | | | | Move CONFIG_FSL_CORENET define to config_mpc85xx.h. It is not board specific feature and belongs to SoC header. Signed-off-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-241-8/+8
|\ | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * i2c, fsl_i2c: switch to new multibus/multiadapter supportHeiko Schocher2013-07-231-8/+8
| | | | | | | | | | | | | | | | | | - added to fsl_i2c driver new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* board/b4860qds: Relax NOR flash teadc timing parameterPrabhakar Kushwaha2013-06-201-1/+1
| | | | | | | Relax parameters to give address latching more time to setup. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/b4860qds: Slave module for boot from SRIO and PCIELiu Gang2013-06-201-5/+27
| | | | | | | | | | | | | | | | | | | | | | When a b4860qds board boots from SRIO or PCIE, it needs to finish these processes: 1. Set all the cores in holdoff status. 2. Set the boot location to one PCIE or SRIO interface by RCW. 3. Set a specific TLB entry for the boot process. 4. Set a LAW entry with the TargetID of one PCIE or SRIO for the boot. 5. Set a specific TLB entry in order to fetch ucode and ENV from master. 6. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 7. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. For more information about the feature of Boot from SRIO/PCIE, please refer to the document doc/README.srio-pcie-boot-corenet. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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