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* mtd: nand: add Freescale vf610_nfc driverStefan Agner2014-09-162-0/+725
| | | | | | | | | | This adds initial support for Freescale NFC (NAND Flash Controller) found in ARM Vybrid SoC's, Power Architecture MPC5125 and others. The driver is called vf610_nfc since this is the first supported and tested hardware platform supported by the driver. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com>
* pcie_imx: Add mx6solox supportFabio Estevam2014-09-091-4/+36
| | | | | | | Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* arm: vf610: lpuart: disable FIFO on initializatonStefan Agner2014-09-091-0/+10
| | | | | | | | | | | | UART does not use the UART FIFO, but we should also not rely that the UART FIFO is diabled by default. For instance, when loading U-Boot using the boot ROMs serial downloader protocol over UART, FIFO is enabled at U-Boot start time. This patch disables the RX and TX FIFO, sets back their thresholds and flushes them. Signed-off-by: Stefan Agner <stefan@agner.ch>
* arm: vf610: lpuart: fix status register handlingStefan Agner2014-09-091-6/+3
| | | | | | | | | | | | | | | | | The status register 1 (S1) is not writeable, hence we should not write it. In order to clear the RDRF flag we only need to read the data register. Also, when stressing U-Boot a lot with serial input, an overflow can occur which asserts the S1_OR flag (while not asserting the S1_RDRF flag). To clear this flag we again just need to read the data register, hence add this flag to the abort conditions for the while loop. Insert a compiler barrier to make sure reading the data register gets executed after reading the status register. Signed-off-by: Stefan Agner <stefan@agner.ch>
* pci: add support for board_pci_fixup_dev functionTim Harvey2014-09-091-0/+4
| | | | | | | Some board-level drivers may wish to have per-device fixup functions for PCI devices. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* sata: dwc_ahsata: implement sata_port_statusNikita Kiryanov2014-09-091-0/+17
| | | | | | | | | | | | Define the new common function sata_port_status() which can be used to query the sata driver for the state of ports, and implement it for dwc_ahsata. Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam2014-09-091-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam2014-09-091-2/+10
| | | | | | | | | | | mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
* Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD2014-09-094-12/+270
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| * video: Add driver for Parade PS8625 dP to LVDS bridgeVadim Bendebury2014-09-052-0/+221
| | | | | | | | | | | | | | | | | | | | | | The initialization table comes from the "Illustration of I2C command for initialing PS8625" document supplied by Parade. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * video: exynos_fimd: Add framework to disable FIMD sysmmuAjay Kumar2014-09-051-0/+43
| | | | | | | | | | | | | | | | | | | | | | On Exynos5420 and newer versions, the FIMD sysmmus are in "on state" by default. We have to disable them in order to make FIMD DMA work. This patch adds the required framework to exynos_fimd driver, and disables FIMD sysmmu on Exynos5420. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * exynos_fb: Remove usage of static definesAjay Kumar2014-09-051-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we used to statically assign values for vl_col, vl_row and vl_bpix using #defines like LCD_XRES, LCD_YRES and LCD_COLOR16. Introducing the function exynos_lcd_early_init() would take care of this assignment on the fly by parsing FIMD DT properties, thereby allowing us to remove LCD_XRES and LCD_YRES from the main config file. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | mtd: nand: omap_gpmc: Fix 'bit-flip' errorsRostislav Lisovy2014-09-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GPMC driver used with some NAND Flash devices (e.g. Spansion S34ML08G1) causes that U-boot shows hundreds of 'nand: bit-flip corrected' error messages. Possible cause was discussed in the mailinglist thread: http://lists.denx.de/pipermail/u-boot/2014-April/177508.html Quote (Author: Pekon Gupta <pekon@ti.com>): "The issue is mainly due to a NAND protocol violation in the omap driver since the Random Data Output command (05h-E0h) expects to see only the column address that should be addressed within the already loaded read page into the read buffer. Only 2 address cycles with ALE active should be provided between the 05h and E0h commands. The Page read command expects the full address footprint (2bytes for column address + 3bytes for row address), but once the page is loaded into the read buffer, Random Data Output should be used with only 2bytes for column address." This patch combines the solution proposed in the mailinglist and the patch provided by the Spansion company (GPLv2 code, source: http://www.spansion.com/Support/Software/u-boot-psp-04.04.00.01-NAND.zip) Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
* | mtd: nand: omap_gpmc: Enable multiple NAND flash devicesRostislav Lisovy2014-09-041-22/+20
| | | | | | | | | | | | | | | | | | | | | | Since the CS of a device connected to the GPMC was stored in the global variable, it was not possible to use multiple devices. In this patch the CS is stored per device in its 'struct omap_nand_info'. This makes it possible to use up to 'GPMC_MAX_CS' NAND Flash devices connected to U-boot. Signed-off-by: Rostislav Lisovy <lisovy@merica.cz>
* | mtd: nand: davinci_nand: correct keystone RBL layout definitionKhoronzhuk, Ivan2014-09-041-1/+1
| | | | | | | | | | | | | | | | In case when 4K page keystone RBL layout is used the compilation error is appeared. That's because the #ifdef has to be placed under struct name. This patch correct it. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan2014-09-041-20/+15
|/ | | | | | | | There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
* USB: gadget: s3c: get rid of debug compile warningBo Shen2014-09-022-8/+8
| | | | | | | | | | When enable debug option to compile, it will give the following warning, this patch is used to get rid of it. --->8--- warning: 'flags' is used uninitialized in this function [-Wuninitialized] ---8<--- Signed-off-by: Bo Shen <voice.shen@atmel.com>
* USB: gadget: atmel: get rid of debug compile warningBo Shen2014-09-021-6/+6
| | | | | | | | | | When enable debug option to compile, it will give the following warning, this patch is used to get rid of it. --->8--- warning: 'flags' is used uninitialized in this function [-Wuninitialized] ---8<--- Signed-off-by: Bo Shen <voice.shen@atmel.com>
* usb: ci_udc: implement dfu_usb_get_resetStephen Warren2014-09-021-0/+7
| | | | | | | | This allows the USB code to determine whether a USB bus reset was issued, which in turn allows the code to differentiate between a detach (return to shell prompt) and a board reset/reboot request. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* udc: dfu: s3c_udc: Provide function to check if USB reset was assertedLukasz Majewski2014-09-021-0/+5
| | | | | | | | | | | New dfu_usb_get_reset() method is necessary to distinct two different use cases of dfu-util program. This method checks if the USB bus reset has been really performed after DFU DETACH. Without this function the previous DFU behavior is preserved. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
* dfu: Provide means to find difference between dfu-util -e and -RLukasz Majewski2014-09-022-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides distinction between DFU device detach and reset. The -R behavior is preserved with proper handling of the dfu-util's -e switch, which detach the DFU device. By running dfu-util -e; one can force device to finish the execution of dfu command on target and execute some other scripted commands. Moreover, some naming has been changed - the dfu_reset() method now is known as dfu_detach(). New name better reflects the purpose of the code. It was also necessary to increase the number of usb_gadget_handle_interrupts() calls since we also must wait for detection of the USB reset event. Example usage: 1. -e (detach) switch dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e access to u-boot prompt. 2. -R (reset) switch dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage target board reset Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-niosTom Rini2014-08-313-3/+143
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| * serial: move nios2-yanu.h into opencores_yanu driverThomas Chou2014-08-301-1/+86
| | | | | | | | | | | | | | | | | | The nios2-yanu.h contains hardware registers and bits of opencores yanu. As there is no other user of this header , it should be moved into the driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> CC: Renato Andreola <renato.andreola@imagos.it>
| * nios2: divide nios2-io.h into each specific drivers and remove itThomas Chou2014-08-302-2/+57
| | | | | | | | | | | | | | | | | | | | The nios2-io.h defines hardware registers and bits of several FPGA IP cores. It could be divided in to the specific drivers, including altera timer, altera sysid, altera uart and altera jtag uart. The altera pio and altera spi drivers use their own hardware definitions. The removal of nios2-io.h will help modularity and maintenance. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | arm/kirkwood/nand: allow forced disabling for subpage writesHolger Brunck2014-08-301-0/+3
| | | | | | | | | | | | | | | | | | | | Make it configurable to disable subpage writes like the DaVinci NAND driver already does. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com> cc: Scott Wood <scottwood@freescale.com>
* | arm: bcm281xx: net: Add Ethernet DriverJiandong Zheng2014-08-305-0/+1535
| | | | | | | | | | | | | | | | | | | | | | The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom SoC(s) and: - supports multiple MAC blocks, - provides support for the Broadcom GMAC. This driver requires MII and PHYLIB. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | socfpga: cleanup socfpga_dw_mmcPavel Machek2014-08-301-4/+4
| | | | | | | | | | | | | | Cleanups as suggested by wd on mailing list. Signed-off-by: Pavel Machek <pavel@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
* | socfpga: fix clock manager register definitionPavel Machek2014-08-291-2/+2
|/ | | | | | | | | Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-08-299-5/+201
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| * pci: mx6: fix occasional link failuresTim Harvey2014-08-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable for SS function) must remain deasserted until the reference clock is running at the appropriate frequency. Without this patch we find a high link failure rate (>5%) on certain IMX6 boards at various temperatures. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-1129-45/+1056
| |\ | | | | | | | | | | | | | | | | | | Conflicts: boards.cfg Signed-off-by: Stefano Babic <sbabic@denx.de>
| * | pmic: pmic_pfuze100: Use a shorter name for PMIC nameFabio Estevam2014-08-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is redundant to use 'PFUZE100_PMIC' as the PMIC name because we already know it is a PMIC. Call it simply 'PFUZE100' instead. Cc: Tim Harvey <tharvey@gateworks.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic2014-08-0839-353/+1286
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| * | | spi: add config option to enable the WP pin function on st micron flashesHeiko Schocher2014-07-232-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable the W#/Vpp signal to disable writing to the status register on ST MICRON flashes like the N25Q128 thorugh the new config option CONFIG_SYS_SPI_ST_ENABLE_WP_PIN Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
| * | | pwm, imx6: add support for pwm modul on imx6Heiko Schocher2014-07-235-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add basic support for the pwm modul found on imx6. Pieces of this code are based on linux code from drivers/pwm/pwm-imx.c Commit "cd3de83f1476 Linux 3.16-rc4" Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
* | | | net: cpsw: am335x: Drop constant link checking from rx/tx path'sStefan Roese2014-08-281-18/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We noticed on the DXR2 platform (AM335x with a SMSC LAN9303 switch connected to the CPSW MAC) that the network performance in U-Boot is quite poor. Only when the transfer is started without a cable connected, and the cable is plugged after the first timeout "T" occured, an increased in performance can be seen. Debugging has revealed, that the cpsw driver has constant link checking builtin into the rx and tx functions. This results in the bad performance and seems to be unnecessary. The link has already been checked in the init function, before the transfer is started. This usually is sufficient. BTW: I have seen no other network driver in U-Boot so far, that constantly checks for link in the rx / tx functions. The performance numbers on the DXR2 board are: 0.56 MiB/s cpsw_check_link() in rx and tx path 0.87 MiB/s cpsw_check_link() only in tx path 1.0 MiB/s cpsw_check_link() only in rx path 2.7 MiB/s no cpsw_check_link() in rx and tx path So with this patch the network performance on DXR2 increases from 0.56 to 2.7 MiB/s (nearly 5 times as fast). Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Samuel Egli <samuel.egli@siemens.com> Tested-by: Heiko Schocher <hs@denx.de> Cc: Vladimir Koutny <vladimir.koutny@streamunlimited.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Tom Rini <trini@ti.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-08-283-0/+218
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| * | | Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD2014-08-093-0/+218
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| | * | | sunxi: add USB EHCI driverRoman Byshko2014-07-312-0/+202
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Allwinner aka sunxi SoCs have one or more USB host controllers. This adds a driver for their EHCI. Signed-off-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | | ahci: provide sunxi SATA driver using AHCI platform frameworkIan Campbell2014-07-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables the necessary clocks, in AHB0 and in PLL6_CFG. This is done for sun7i only since I don't have access to any other sunxi platforms with sata included. The PHY setup is derived from the Alwinner releases and Linux, but is mostly undocumented. The Allwinner AHCI controller also requires some magic (and, again, undocumented) DMA initialisation when starting a port. This is added under a suitable ifdef. This option is enabled for Cubieboard, Cubieboard2 and Cubietruck based on contents of Linux DTS files, including SATA power pin config taken from the DTS. All build tested, but runtime tested on Cubieboard2 and Cubietruck only. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | | mtd,ubi,ubifs: sync with linux v3.15Heiko Schocher2014-08-257-47/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | snyc with linux v3.15: commit 1860e379875dfe7271c649058aeddffe5afd9d0d Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Jun 8 11:19:54 2014 -0700 Linux 3.15 Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* | | | | mtd, ubi, ubifs: update for the sync with linux v3.14Heiko Schocher2014-08-252-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | while playing with the new mtd/ubi/ubifs sync, found some small updates for it: - add del_mtd_partition() to include/linux/mtd/mtd - mtd: add a debug_printf - remove some not used functions Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Scott Wood <scottwood@freescale.com> Cc: Tom Rini <trini@ti.com>
* | | | | mtd, ubi, ubifs: resync with Linux-3.14Heiko Schocher2014-08-2537-4438/+10961
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | resync ubi subsystem with linux: commit 455c6fdbd219161bd09b1165f11699d6d73de11c Author: Linus Torvalds <torvalds@linux-foundation.org> Date: Sun Mar 30 20:40:15 2014 -0700 Linux 3.14 A nice side effect of this, is we introduce UBI Fastmap support to U-Boot. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Sergey Lapin <slapin@ossfans.org> Cc: Scott Wood <scottwood@freescale.com> Cc: Joerg Krause <jkrause@posteo.de>
* | | | | lib, linux: move linux specific defines to linux/compat.hHeiko Schocher2014-08-255-68/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - move linux specific defines from usb and video code into linux/compat.h - move common linux specific defines from include/ubi_uboot.h to linux/compat.h - add for new mtd/ubi/ubifs sync new needed linux specific defines to linux/compat.h Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Anatolij Gustschin <agust@denx.de> [trini: Add spin_lock_irqsave/spin_unlock_irqrestore dummies from usb/lin_gadet_compat.h] Signed-off-by: Tom Rini <trini@ti.com>
* | | | | Merge branch 'agust@denx.de' of git://git.denx.de/u-boot-stagingTom Rini2014-08-253-2/+3
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| * | | | | RTC: add support for DS1339 (using DS1307 driver)Markus Niebel2014-08-142-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
| * | | | | driver/qe: update status of QE microcodevijay rai2014-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Patch updates error print for QE which should be easily understood Signed-off-by: Vijay Rai <vijay.rai@freescale.com>
| * | | | | pci: fix overflow in __pci_hose_bus_to_phys w/ large RAMStephen Warren2014-08-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a 32-bit system has 2GB of RAM, and the base address of that RAM is 2GB, then start+size will overflow a 32-bit value (to a value of 0). To avoid such an overflow, convert __pci_hose_bus_to_phys() to calculate the offset of a bus address into a PCI region, rather than comparing a bus address against the end of a PCI region. Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | | | | | e1000: add i210 supportMarek Vasut2014-08-212-27/+180
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add i210 support to the e1000 driver. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
* | | | | | e1000: Implement dcache supportMarek Vasut2014-08-211-22/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement proper support for cache flushing and invalidation into the Intel e1000 NIC driver. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Tim Harvey <tharvey@gateworks.com>
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