summaryrefslogtreecommitdiffstats
path: root/drivers
Commit message (Collapse)AuthorAgeFilesLines
* x86: Move VGA option rom macros to KconfigBin Meng2015-07-141-2/+2
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* video: Add 32-bit color depth support for VBEJian Luo2015-07-141-0/+1
| | | | | | | | | | The TunnelCreek IGD VBE reports 32-bit color depth regardless 24-bit color depth is configured. Since 24-bit mode already uses 4 bytes internally, it should be OK to just add this option in switch case. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* video: vesa_fb: Look up VGA device by class instead of idBin Meng2015-07-141-14/+2
| | | | | | | | | Per PCI spec, VGA device reports its class as standard 030000h in its configuration space, so we can use it to determine if we need run option rom instead of testing the supported vendor/device ids. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Correct bus number when scanning sub-busesSimon Glass2015-07-141-1/+1
| | | | | | | The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it so that sub-buses are numbered correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: pci: Use the correct hose when configuring devicesSimon Glass2015-07-142-1/+11
| | | | | | | | | | | | | Only the PCI controller has access to the PCI region information. Make sure to use the controller (rather than any attached bridges) when configuring devices. This corrects a failure to scan and configure devices when driver model is enabled for PCI. Also add a comment to explain the problem. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: rtc: Support mc146818 driver in driver modelBin Meng2015-07-141-108/+204
| | | | | | | | Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move MP initialization codes into a common placeBin Meng2015-07-141-0/+2
| | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-141-0/+10
| | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: cpu: Test against cpu_ops->get_info in cpu_get_info()Bin Meng2015-07-141-1/+1
| | | | | | | In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: cpu: Fix undefined ENOSYS build errorBin Meng2015-07-141-0/+1
| | | | | | | Include <errno.h> otherwise ENOSYS is undefined. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: spi: Correct minor nits in ICH driverSimon Glass2015-07-141-3/+2
| | | | | | | | Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* Merge git://git.denx.de/u-boot-samsungTom Rini2015-07-101-1/+1
|\
| * exynos: i2c: Correct bug in pinmux selectionSimon Glass2015-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When driver model is not used the current code does not correctly select the pinmux for the I2C bus. This bug was introduced by this commit: 8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-103-8/+56
|\ \
| * | usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-101-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | block: ahci: Don't enable port interruptsStefan Roese2015-07-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the initialization of the AHCI controller to not enable the default interrupts (DEF_PORT_IRQ). As interrupts are not used in U-Boot in general, this should not break the common AHCI driver operation. This change is needed to support the Marvell Armada 38x AHCI controller. With interrupts enabled, this results in timeouts in ahci_device_data_io(). Not enabling these interrupts fixes this problem and the common AHCI driver works fine. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | mmc: sdhci.c: Add config option to use a fixed buffer for transfersStefan Roese2015-07-101-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the following problem occured. The SPL runs in internal SRAM which is the L2 cache locked to memory. When the MMC buffers now are located on the stack (or bss), the SDIO controller (SDHCI) can't write into this L2 cache memory. This patch introduces a method to use a fixed buffer that will be used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER. This way, the board can use this buffer address located in SDRAM for all transfers. This solves this SPL problem on the A38x and should only be used in the SPL U-Boot version. Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | mmc: sdhci: Use timer based timeout detection in sdhci_send_command()Stefan Roese2015-07-101-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | The loop counter based timeout detection does not work on the Armada 38x based board (DB-88F6820-GP). At least with dcache enabled a timeout is detected. Without dcache enabled, the timeout does not occur. Increasing the loop counter solves this issue. But a better solution is to use a timer based timeout detection instead. This patch now implements this timer based detection. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada2015-07-101-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ahci: Fix compiling warnings under 64bit platformsTang Yuantian2015-07-092-34/+43
|/ | | | | | | | | | | | | | | | | | | | When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* net: designware: Program MAC address to hardware after soft resetBin Meng2015-07-081-0/+6
| | | | | | | | | | commit f566c99 "net: Update hardware MAC address if it changes in env" removes writing MAC address to designware controller after soft reset. This makes designware ethernet port fail to work. Actually the MAC address should always be programmed after soft reset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-072-20/+35
|\
| * arm: dcc: Add uart dcc support for armv8Siva Durga Prasad Paladugu2015-07-071-0/+16
| | | | | | | | | | | | | | | | Added UART DCC support for armv8 Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-0748-797/+2019
| |\
| * | gpio: lpc32xx: Use priv_data instead of platdataAxel Lin2015-07-071-20/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | The LPC32XX GPIO driver platdata currently contains GPIO state information, which should go into priv_data. Thus rename lpc32xx_gpio_platdata to lpc32xx_gpio_priv and convert to use dev_get_priv() instead. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
* | | spi: cf_qspi: fix clamp macro type check compilation warningsAngelo Dureghello2015-07-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix compilation warnings for redefined 'clamp' macro and non-uniform clamp macro types. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
* | | sf: Kconfig: Add SPI_FLASH_BAR entryJagan Teki2015-07-011-0/+8
| | | | | | | | | | | | | | | | | | Added SPI_FLASH_BAR entry on Kconfig with help description Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | spi: Kconfig: Add TEGRA20_SLINK entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA20_SLINK entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* | | spi: Kconfig: Add TEGRA20_SFLASH entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA20_SFLASH entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* | | spi: Kconfig: Add TEGRA114_SPI entryJagan Teki2015-07-011-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added TEGRA114_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Warren <twarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com>
* | | spi: Kconfig: Add ICH_SPI entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Added ICH_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | spi: Kconfig: Add EXYNOS_SPI entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | Added EXYNOS_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | spi: Kconfig: Add FSL_QSPI entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Added FSL_QSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* | | spi: Kconfig: Add FSL_ESPI entryJagan Teki2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | | | Added FSL_ESPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* | | spi: Kconfig: Add FSL_DSPI entryJagan Teki2015-07-011-0/+8
| | | | | | | | | | | | | | | | | | | | | Added FSL_DSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Haikun Wang <haikun.wang@freescale.com>
* | | spi: Kconfig: Show dm-spi drivers if DM_SPI setJagan Teki2015-07-011-25/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DM supported spi drivers are enbled only when DM_SPI enabled, so added DM_SPI if condition in Kconfig to show thoese only when it enabled. Also re-order the config items as incresing alphabetic order. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | spi: Makefile: Use object file alphabetic orderJagan Teki2015-07-011-5/+5
| | | | | | | | | | | | | | | | | | | | | Use object files as incresing alphabetic order, so-that it's easy for readability. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | spi: Kconfig: Add TI_QSPI entryJagan Teki2015-07-011-0/+6
| | | | | | | | | | | | | | | | | | | | | Added TI_QSPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | spi: Kconfig: Add XILINX_SPI entryJagan Teki2015-07-011-0/+9
| | | | | | | | | | | | | | | | | | | | | Added XILINX_SPI entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* | | spi: Add Kconfig menu entryJagan Teki2015-07-011-0/+4
| | | | | | | | | | | | | | | | | | Added Kconfig menu ... endmenu enties for spi support. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | sf: Kconfig: Add SPI_FLASH_DATAFLASH entryJagan Teki2015-07-012-10/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added SPI_FLASH_DATAFLASH entry on Kconfig with help description. data flash driver comes with good decription, hence moved the same on to kconfig help decription. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Haikun Wang <haikun.wang@freescale.com>
* | | sf: Kconfig: Add SPI_FLASH_MTD entryJagan Teki2015-07-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Added SPI_FLASH_MTD entry on Kconfig with help description. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Heiko Schocher <hs@denx.de>
* | | sf: Kconfig: Update SPI_FLASH entryJagan Teki2015-07-011-9/+9
| | | | | | | | | | | | | | | | | | | | | Updated SPI_FLASH entry on Kconfig with depends on and along with config help description. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | sf: Add Kconfig menu entryJagan Teki2015-07-011-0/+4
| | | | | | | | | | | | | | | | | | Added Kconfig menu ... endmenu enties for spi flash suppor Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | sf: dataflash: Rename to CONFIG_SPI_FLASH_DATAFLASHJagan Teki2015-07-011-1/+1
| | | | | | | | | | | | | | | | | | | | | Rename CONFIG_SF_DATAFLASH into CONFIG_SPI_FLASH_DATAFLASH as it follows the naming convention same as remaining configs. Signed-off-by: Jagan Teki <jteki@openedev.com>
* | | spi: Kconfig: Add Zynq SPI controller entryJagan Teki2015-07-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Zynq SPI controller Kconfig entry. Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* | | spi: xilinx_spi: Add asm/io.h include fileJagan Teki2015-07-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes asm/io.h for readl and writel calls. build errors: drivers/spi/xilinx_spi.c: In function 'xilinx_spi_probe': drivers/spi/xilinx_spi.c:119:2: warning: implicit declaration of function 'writel' [-Wimplicit-function-declaration] drivers/spi/xilinx_spi.c: In function 'xilinx_spi_xfer': drivers/spi/xilinx_spi.c:193:2: warning: implicit declaration of function 'readl' [-Wimplicit-function-declaration] Signed-off-by: Jagan Teki <jteki@openedev.com> Cc: Michal Simek <michal.simek@xilinx.com>
* | | dm: spi: xilinx_spi: Convert to driver modelJagan Teki2015-07-011-88/+112
| | | | | | | | | | | | | | | | | | | | | | | | This converts the xilinx spi driver to use the driver model. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com>
* | | spi: zynq_spi: Add fdt support in driverJagan Teki2015-07-011-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now zynq spi driver platform data is controlled by devicetree, enable the status by saying "okay" on respective board dts to use the devicetree generated platdata. Ex: &spi1 { status = "okay"; }; Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
* | | dm: spi: zynq_spi: Convert to driver modelJagan Teki2015-07-011-124/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This converts the zynq spi driver to use the driver model. Minimal functional changes like using meaningful name on structure members wrt mainlined dm spi drivers. - input_hz -> frequency - req_hz -> freq - base -> regs Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
OpenPOWER on IntegriCloud