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| * | usb: gadget: f_thor: Allocate request up to THOR_PACKET_SIZESiva Durga Prasad Paladugu2015-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allocate request up to THOR_PACKET_SIZE not the ep0->maxpacket as the descriptors data depend on the number of descriptors and this 64 bytes were not enough and the buffer might overflow which results in memalign failures later. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | f_thor: Dont perform reset at the end of thorSiva Durga Prasad Paladugu2015-09-072-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dont perform reset at the end of thor download if configured to do reset off. Reset may not be required in all cases and hence provided an option to do so. The case would be to download the images to DDR instead of flash device. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | net: altera_tse: Zap unused variableMarek Vasut2015-09-041-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Zap variable which is set but never used. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Tested-by: Thomas Chou <thomas@wytron.com.tw>
* | | mmc: dw_mmc: Probe the MMC from OFMarek Vasut2015-09-041-13/+68
|/ / | | | | | | | | | | | | | | | | | | | | | | | | Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-0337-22/+2650
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| * | mmc: Probe DM based mmc devices in u-bootSjoerd Simons2015-09-021-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | During mmc initialize probe all devices with the MMC Uclass if build with CONFIG_DM_MMC Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add SPI driverSimon Glass2015-09-024-0/+507
| | | | | | | | | | | | | | | | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add I2C driverSimon Glass2015-09-023-0/+401
| | | | | | | | | | | | | | | | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add an MMC driverSimon Glass2015-09-023-0/+108
| | | | | | | | | | | | | | | | | | | | | Add an MMC driver which supports RK3288, but may also support other SoCs. It uses the Designware MMC device. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add pinctrl driverSimon Glass2015-09-024-0/+459
| | | | | | | | | | | | | | | | | | | | | Add a driver which supports pin multiplexing setup for the most commonly used peripherals. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock driverSimon Glass2015-09-022-0/+619
| | | | | | | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | power: regulator: Add a driver for ACT8846 regulatorsSimon Glass2015-09-023-0/+165
| | | | | | | | | | | | | | | | | | | | | Add a full regulator driver for the ACT8846. This provides easy access to voltage and current settings for each regulator. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | power: Add support for ACT8846 PMICSimon Glass2015-09-023-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and is connected to the I2C bus. This driver supports using a regulator driver to access the regulators. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-023-0/+133
| | | | | | | | | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add serial supportSimon Glass2015-09-023-0/+53
| | | | | | | | | | | | | | | | | | | | | Add support for the Rockchip serial device using the ns16550 driver. This uses driver model and device tree for both SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Provide better debugging when a device fails to bindSimon Glass2015-09-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All devices should bind without error. But when they don't, they can cause driver model init to fail. A real situation where this can happen is when there is a missing uclass. Add a debug() call to dm_scan_fdt_node to make this easier to track. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Improve handling of a missing uclassSimon Glass2015-09-022-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a uclass definition is missing, no drivers in that uclass can operate. This can happen if a board has a strange collection of options (e.g. the driver is enabled but the uclass is not). Unfortunately this is very confusing at present. Starting up driver model results in a -ENOENT error, which is pretty generic. Quite a big of digging is needed to get to the root cause. To help with this, change the error to a very strange one with no other users in U-Boot. Also add a debug message. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | mmc: Support bypass mode with the get_mmc_clk() methodSimon Glass2015-09-022-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some SoCs want to adjust the input clock to the DWMMC block as a way of controlling the MMC bus clock. Update the get_mmc_clk() method to support this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jaehoon Chung <jh80.chung@samsung.com>
| * | dm: led: Tidy up SPL options for the led and led-gpioSimon Glass2015-09-022-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | At present SPL does not have its own option. But these features can increase SPL code size. Adjust the Kconfig and Makefile so that separate a SPL option can be selected. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: Add the concept of peripheral IDsSimon Glass2015-09-021-9/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My original pinctrl patch operating using a peripheral ID enum. This was shared between pinmux and clock and provides an easy way to specify a device that needs to be controlled, even it is does not (yet) have a driver within driver model. Masahiro's new simple pinctrl gets around this by providing a set_state_simple() pinctrl method. By passing a device to that call the peripheral ID becomes unnecessary. If the driver needs it, it can calculate it itself and use it internally. However this does not solve the problem for peripheral clocks. The 'pure' solution would be to pass a driver to the clock uclass also. But this requires that all devices should have a driver, and a struct udevide. Also a key optimisation of the clock uclass is allowing a peripheral clock to be set even when there is no device for that clock. There may be a better way to achive the same goal, but for now it seems expedient to add in peripheral ID to the pinctrl uclass. Two methods are added - one to get the peripheral ID and one to select it. The existing set_state_simple() is effectively the union of these. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | pinctrl: Add help text to KconfigSimon Glass2015-09-021-1/+10
| | | | | | | | | | | | | | | | | | | | | The pinctrl Kconfig options should have help messages. Add this to a few options. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | powerpc: ppc4xx: remove lwmon5 supportMasahiro Yamada2015-09-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Remove CONFIG_LWMON5 references. (Also, remove undefined CONFIG_WD_MAX_RATE while I am here.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Stefan Roese <sr@denx.de>
* | | serial: drop redundant depends onMasahiro Yamada2015-09-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SANDBOX_SERIAL depends on SANDBOX, and SANDBOX selects DM. So, "SANDBOX_SERIAL depends on DM" is redundant. Likewise, UNIPHIER_SERIAL depends on ARCH_UNIPHIER, and ARCH_UNIPHIER selects DM_SERIAL. So, "UNIPHIER_SERIAL depends on DM_SERIAL" is redundant. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-09-021-7/+20
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| * | | net/fman: Support both new and legacy FMan CompatiblesIgal Liberman2015-09-011-7/+20
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently the FMan Port and MAC compatibles were changed. This patch aligns the FMan Port and MAC compatibles to the new FMan device tree binding document. The FMan device tree binding document can be found in the Linux kernel: ./Documentation/devicetree/bindings/powerpc/fsl/fman.txt This patch doesn't affect legacy compatibles support. Signed-off-by: Igal Liberman <igal.liberman@freescale.com> Tested-by: Xing Lei <xing.lei@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-027-15/+196
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| * | | mxc: ocotp fix hole in shadow registersPeng Fan2015-09-021-5/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | video, lg4573: make spi bus and cs configurableHeiko Schocher2015-09-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make the spi bus and the spi chipselect configurable for the lg4573 driver. Use it on the aristainetos boards. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
| * | | imx: ocotp: mxc add i.MX7D supportAdrian Alonso2015-09-021-1/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Ocotp of i.MX7D has different operation rule. This patch is to add support for i.MX7D ocotp. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-021-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | | power: pmic: add pfuze3000 supportAdrian Alonso2015-09-022-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add pmic pfuze3000 support, implement power_pfuze3000_init to be used in power_init_board callback function. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | | net: fec: do not access reserved register for i.MX6ULPeng Fan2015-09-021-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIB RAM and FIFO receive start register does not exist on i.MX6UL. Accessing these register will cause enet not work well. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | mxs_ocotp: Shift the HBUS divider correctlyChris Smith2015-09-021-0/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the original HBUS divider value is retrieved in mxs_ocotp_scale_hclk() for the purpose or restoring it back later, the value is not shifted by the HBUS divider offset in that register. This is not a problem, since the shift is zero on all MXS hardware. Add the shift anyway, for completeness and in case FSL ever decides to re-use this driver on future designs. Signed-off-by: Chris Smith <chris@zxdesign.info> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
* | | pci/layerscape: Setup mmu-masters property for the PCIeVarun Sethi2015-09-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Setup mmu-masters property for the PCIe controllers. This would be used by the Linux SMMU driver, while setting up stream ID table mappings for the PCIe devices. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-012-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-011-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | driver: misc: debug server: Update Error messagePrabhakar Kushwaha2015-09-011-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Append "debug server FW" in error message to make more informative. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | net: phy/vitesse: Add support for VSC8584 phyPrabhakar Kushwaha2015-09-011-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of VSC8584 phy placed on new QSGMII/SGMII ethernet riser cards used on LS2085QDS platforms. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | rtc:ds3232/ds3231: Add support to generate 32KHz outputPriyanka Jain2015-09-011-0/+10
|/ / | | | | | | | | | | | | | | | | | | | | | | RTC devices can generate 32KHz output if for -DS3232 device, EN32KHz bit and BB32KHz bit are set -DS3231 device, EN32KHz bit is set, BB32KHz bit is don't care Patch adds rtc_enable_32khz_output() which when called will enable 32KHz output on 32KHz pin Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-08-316-159/+187
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| * | sunxi: mmc: set transfer timeout according to byte_cnt.Yousong Zhou2015-08-311-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Originally a timeout value of 2 seconds was used regardless of the size of data to be transfered. This prevented slow devices from working correctly while there was no much gain for faster devices, e.g. it takes 3708ms for a transfer of uImage of size 1899008 bytes. Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | mtd: nand: Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through KconfigHans de Goede2015-08-311-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make CONFIG_SYS_NAND_U_BOOT_OFFS configurable through Kconfig, just like SYS_NAND_BUSWIDTH_16BIT this is only enabled on some SoCs using depends, to avoid double defining it for SoCs which have not yet moved to Kconfig for this. Having this in Kconfig is useful because this is something which may differ from one board to the other even when using the same SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Scott Wood <scottwood@freescale.com>
| * | sunxi_nand_spl: clear status flags in SPL implementationBoris Brezillon2015-08-311-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some status flags remain set until you explicetly clear the bit in the status register. Fix the SPL implementation to avoid false positive. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> [hdegoede@redhat.com: Port from v2015.07 to v2015.10] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi_nand_spl: Remove NAND_SUNXI_SPL_SYNDROME_PARTITIONS_ENDHans de Goede2015-08-312-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only ever use syndrome mode for the partitions which contain the SPL, as that is required for the BROM to be able to read the SPL. Instead of using some arbritray limit for deciding whether or not to use syndrome, be smart and check if u-boot-dtb.bin is directly behind the SPL, if it is not then it is on its own partition and we should not use syndrome. Note the reason why we only use syndrome mode for the SPL is because it comeswith weaker randomization, introducing a risk for more bit errors, so we want to avoid it when possible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXIHans de Goede2015-08-312-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We eventually want to add full nand support, since it makes no sense to build SPL with nand support and u-boot without, or the other way around, a single option will suffice. Renaming the Kconfig option now makes things easier when we add full nand support in the future. The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an "ifdef CONFIG_SPL_BUILD" block in the Makefile. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Add support for backup boot partitionsHans de Goede2015-08-311-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BROM does not care / use bad page markings, instead it deals with any bad pages in the first erase-block by simply trying to load "boot0" from the next erase-block. This commit implements the same strategy for the sunxi spl nand code, allowing it to boot from the backup boot partition when the main boot partition is bad (tested by erasing the main boot partition). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Auto detect nand configuration parametersHans de Goede2015-08-312-29/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Auto detect the nand configuration parameters, like the BROM does. This allows us to get rid of various Kconfig settings, and is necessary to support generic boards like the mk802 which have seen many production runs with different nands. The full blown u-boot/kernel nand driver uses the nand id to determine this info, for the SPL we do as the BROM does and simply try a few standard configs. Note the table only contains configs which are known to actually be used, rather then all the configs the BROM tries. This means that it may need to be updated in the future as we add support for nand on more boards. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Parametrize lowlevel read functionsHans de Goede2015-08-311-38/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parametrize the lowlevel nand_read_page function, instead of directly using the CONFIG_foo settings for page-size, etc. there and add a few wrappers / helper functions for calling it. This is a preparation patch for adding auto-detecting of the nand parameters like the BROM does. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Properly config page-size in the nand ctl registerHans de Goede2015-08-311-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Properly config page-size in the nand ctl register, it seems that things work fine without doing this, but still lets play it safe and properly set the page-size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sunxi_nand_spl: Add support for sun4i and sun5i SoCsHans de Goede2015-08-311-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Other then having a few less chip-select lines the nand controller on sun4i, sun5i and sun7i is identical. Note this patch also muxes GPC7 to the NAND on sun7i where as before it was not muxed this way. GPC7 is a standard NAND pin, so it should always be muxed to the NAND when in use. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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