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path: root/drivers/spi/zynq_qspi.c
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* spi: zynq_qspi: Add configuration to disable LQSPI featureNathan Rossi2015-12-181-0/+9
| | | | | | | | | | | | | | | | When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* spi: zynq_[q]spi: Use GENMASK macroJagan Teki2015-10-271-4/+4
| | | | | | | | | | | GENMASK macro used on zynq_spi.c and zynq_qspi.c GENMASK is used to create a contiguous bitmask([hi:lo]). Ex: (0x7 << 3) => GENMASK(5, 3) Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_[q]spi: Use BIT macroJagan Teki2015-10-271-10/+10
| | | | | | | | | | | | Used BIT macro on zynq_spi.c and zynq_qspi.c :%s/(1 << nr)/BIT(nr)/g where nr = 0, 1, 2 .... 31 Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_qspi: Minor cleanupsJagan Teki2015-10-251-5/+3
| | | | | | | | - Use __func__ on debug - Removed unnecessary comment - Fix function name in debug as zynq_qspi_xfer instead of spi_xfer Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: zynq_qspi: Fix to configure CPOL, CPHA maskJagan Teki2015-10-251-3/+4
| | | | | | | | | | | | | priv->mode is initialized when .set_speed triggers with mode value, so checking mode for configuring CPOL, CPHA using priv->mode is invalid hence use mode from .set_speed argument, and at the end priv->mode will initialized with mode. This patch also replaces formatting string to use speed instead of mode in .set_speed ops. Signed-off-by: Jagan Teki <jteki@openedev.com>
* spi: Add zynq qspi controller driverJagan Teki2015-10-251-0/+622
Added zynq qspi controller driver for Xilinx Zynq APSOC, this driver is driver-model driven with devicetree support. => sf probe SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB => mw.b 0x100 0xCC 0x1000000 => sf update 0x100 0x0 0x1000000 device 0 whole chip 16777216 bytes written, 0 bytes skipped in 59.842s, speed 289262 B/s => sf read 0x3000000 0x0 0x1000000 device 0 whole chip SF: 16777216 bytes @ 0x0 Read: OK => cmp.b 0x3000000 0x100 0x1000000 Total of 16777216 byte(s) were the same Signed-off-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
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