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path: root/drivers/mtd/nand/fsl_elbc_nand.c
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* nand/fsl_elbc: Convert to self-initScott Wood2012-01-261-5/+38
| | | | | | | | This driver doesn't yet make use of the added flexibility (not that that should stop anyone from converting...), but it will with the in-progress hack to support 4k-page NAND. Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd/nand: Add ONFI support for FSL NAND controllerShengzhou Liu2012-01-261-7/+10
| | | | | | | | - fix NAND_CMD_READID command for ONFI detect. - add NAND_CMD_PARAM command to read the ONFI parameter page. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* mtd: eLBC NAND: remove elbc_fcm_ctrl->oob_poimhench2011-10-031-30/+2
| | | | | | | | | | | | | The eLBC NAND driver currently follows up each program/write operation with a read-back of the page, in order to [ostensibly] fill in ECC data for the caller. However, the page address used for this read is always -1, so the read will never work correctly. Remove this useless (and potentially problematic) block of code. v2: fix broken mailer Signed-off-by: mhench <mhench@elutions.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-161-11/+7
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_elbc_nand: remove the bbt descriptors relocation fixupMingkai Hu2009-11-131-4/+0
| | | | | | | The commit 66372fe2 manually relocated the bbt pattern pointer, which can be removed by using full relocation. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
* NAND: ADD page Parameter to all read_page/read_page_raw API'sSandeep Paulraj2009-08-261-1/+1
| | | | | | | | | | | | | | | | This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: redirect the pointer of bbt pattern to RAMMingkai Hu2009-07-071-0/+4
| | | | | | | | | | | The bbt descriptors contains the pointer to the bbt pattern which are statically initialized memory struct. When relocated to RAM, these pointers will continue point to NOR flash(or L2 SRAM, or other boot device). If the contents of NOR flash changed or L2 SRAM disabled, it'll hang the system. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* NAND FSL elbc: Use virt_to_phys to determine which bank is in useKumar Gala2008-12-191-2/+4
| | | | | | | | | | | | | The current code that determines which bank/chipselect is used for a given NAND instance only worked for 32-bit addresses and assumed a 1:1 mapping. This breaks in 36-bit physical configs. The proper way to handle this is to use the virt_to_phys() and BR_PHYS_ADDR() routinues to match the 34-bit lbc bus address with the the virtual address the NAND code uses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Scott Wood <scottwood@freescale.com>
* NAND fsl elbc: Set FMR[ECCM] based on page size.Scott Wood2008-10-291-2/+14
| | | | | | | Hardware expects ECCM 0 for small page and ECCM 1 for large page when booting from NAND, so use those defaults. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-291-9/+11
| | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* fsl_elbc_nand: ecclayout cleanupsAnton Vorontsov2008-09-121-4/+0
| | | | | | | | | | This patch deletes oobavail assignments, they're calculated by the nand core code in nand_scan_tail, plus current oobavail values are wrong for the LP NANDs. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: implement support for flash-based BBTAnton Vorontsov2008-09-121-1/+34
| | | | | | | | | | | | | This patch implements support for flash-based BBT for chips working through ELBC NAND controller, so that NAND core will not have to re-scan for bad blocks on every boot. Because ELBC controller may provide HW-generated ECCs we should adjust bbt pattern and bbt version positions in the OOB free area. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: fix OOB workability for large page NAND chipsAnton Vorontsov2008-09-121-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For large page chips, nand_bbt is looking into OOB area, and checking for "0xff 0xff" pattern at OOB offset 0. That is, two bytes should be reserved for bbt means. But ELBC driver is specifying ecclayout so that oobfree area starts at offset 1, so only one byte left for the bbt purposes. This causes problems with any OOB users, namely JFFS2: after first mount JFFS2 will fill all OOBs with "erased marker", so OOBs will contain: OOB Data: ff 19 85 20 03 00 ff ff ff 00 00 08 ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff OOB Data: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff And on the next boot, NAND core will rescan for bad blocks, then will see "0xff 0x19" pattern, and will mark all blocks as bad ones. To fix the issue we should implement our own bad block pattern: just one byte at OOB start. Though, this will work only for x8 chips. For x16 chips two bytes must be checked. Since ELBC driver does not support x16 NANDs (yet), we're safe for now. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-08-141-49/+49
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* fsl_elbc_nand: Hard-code the FBAR/FPAR split.Scott Wood2008-08-121-3/+2
| | | | | | | | The hardware has separate registers for block and page-within-block, but the division between the two has no apparent relation to the actual erase block size of the NAND chip. Signed-off-by: Scott Wood <scottwood@freescale.com>
* fsl_elbc_nand: workaround for hangs during nand writeAnton Vorontsov2008-08-121-1/+10
| | | | | | | | Using current driver elbc sometimes hangs during nand write. Reading back last byte helps though (thanks to Scott Wood for the idea). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* Freescale eLBC FCM NAND driverScott Wood2008-08-121-0/+759
This is a driver for the Flash Control Machine of the enhanched Local Bus Controller found on some Freescale chips (such as the mpc8313 and the mpc8379). Signed-off-by: Scott Wood <scottwood@freescale.com>
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