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* mtd: atmel_nand: according to pmecc version to perform 0xff page correctionWu, Josh2015-02-071-0/+20
| | | | | | | | | | | | As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip can generate 0xff pmecc ECC value for all 0xff sector. According to this, add PMECC version check, if it's SAMA5D4 then we always let PMECC hardware to correct it. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel_nand: runtime to build gf table for pmeccJosh Wu2014-11-171-0/+4
| | | | | | | | | | | | | | | As in SAMA5D4 SoC, the gf table in ROM code can not be seen. So, when we try to use PMECC, we need to build it when do initialization. Add a macro NO_GALOIS_TABLE_IN_ROM in soc header file. If it is defined we will build gf table runtime. The PMECC use the BCH algorithm, so based on the build_gf_tables() function in lib/bch.c, we can build the Galois Field lookup table. Signed-off-by: Josh Wu <josh.wu@atmel.com> Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* mtd: atmel-nand: use pmecc_readl(b)/pmecc_writel to access the pmecc registerWu, Josh2014-09-191-0/+3
| | | | | | | | | | We defined the macro pmecc_readl(b)/pmecc_writel for pmecc register access. But in the driver we also use the readl(b)/writel. To keep consistent, this patch make all use pmecc_readl(b)/pmecc_writel. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-4/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* at91: atmel_nand: Update driver to support Programmable Multibit ECC controllerWu, Josh2012-09-011-0/+113
| | | | | | | | | | | | | | | | | | The Programmable Multibit ECC (PMECC) controller is a programmable binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder. This controller can be used to support both SLC and MLC NAND Flash devices. It supports to generate ECC to correct 2, 4, 8, 12 or 24 bits of error per sector of data. To use PMECC in this driver, the user needs to set the PMECC correction capability, the sector size and ROM lookup table offsets in board config file. This driver is ported from Linux kernel atmel_nand PMECC patch. The main difference is in this version it uses registers structure access hardware instead of using macros. It is tested in 9x5 serial boards. Signed-off-by: Josh Wu <josh.wu@atmel.com> [rebase] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* at91: add hwecc method for nandNikolay Petukhov2010-03-231-0/+36
This is a patch to use the hardware ECC controller of the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33. Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
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