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* dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-281-9/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
* i2c: mxc: add a condition in case the parameter is NULLGong Qianyu2016-01-031-2/+10
| | | | | | | | | | | | | | | | This could avoid executing the code that only applies to i.MX platforms. The bus_i2c_init() is called before relocation and will assgin value to a static variable. If U-Boot is then still running in a flash device, it's theoretically not allowed to write data to flash without an erasing operation. For i.MX platforms, the U-Boot is always running in DDR. Actually it causes asynchronous error when the ARM64 system error report is enabled and the flash write protect is set. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu2015-10-291-2/+2
| | | | | | | | | | | | | There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* I2C: mxc_i2c: make I2C1 and I2C2 optionalAlbert ARIBAUD \\(3ADEV\\)2015-10-021-0/+6
| | | | | | | | | | | | | | | | | | | The driver assumed that I2C1 and I2C2 were always enabled, and if they were not, then an asynchronous abort was (silently) raised, to be caught much later on in the Linux kernel. Fix this by making I2C1 and I2C2 optional just like I2C3 and I2C4 are. To make the change binary-invariant, declare I2C1 and I2C2 in every include/configs/ file which defines CONFIG_SYS_I2C_MXC. Also, while updating README about CONFIG_SYS_I2C_MXC_I2C1 and CONFIG_SYS_I2C_MXC_I2C2, add missing descriptions for I2C4 speed (CONFIG_SYS_MXC_I2C4_SPEED) and slave (CONFIG_SYS_MXC_I2C4_SLAVE) config options. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-101-1/+2
| | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
* i2c, mxc: rework i2c base address names for different SoCsHeiko Schocher2015-05-261-25/+24
| | | | | | | rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
* arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-261-0/+3
| | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
* i2c: mxc: refactor i2c driver and support dmPeng Fan2015-05-141-185/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Introduce a new structure `struct mxc_i2c_bus`, this structure will used for non-DM and DM. 2. Remove `struct mxc_i2c_regs` structure, but use register offset to access registers based on `base` entry of `struct mxc_i2c_bus`. 3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform flags. A new flag is introduced, I2C_QUIRK_FLAG. 4. Most functions use `struct mxc_i2c_bus` as one of the parameters. Make most functions common to DM and non-DM, try to avoid duplicated code. 5. Support DM, but pinctrl is not included. Pinmux setting is still set by setup_i2c, but we do not need bus_i2c_init for DM. 6. struct i2c_parms and struct sram_data are removed. 7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist paramter of bus_i2c_init is modified to i2c index. Add new prototype i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus. Board file take the responsibility to implement this function, like this: " int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) { if (i2c_bus->index == 0) force_bus_idle(i2c_pads_info0); else if (i2c_bus->index == 1) force_bus_idle(i2c_pads_info1); else xxxxxx } " 8. Introduce a weak function, enable_i2c_clk 9. Tested on an i.MX7 platform. Log info: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ ] |-- soc simple_bus [ ] | |-- aips-bus@30000000 simple_bus [ ] | | |-- anatop@30360000 simple_bus [ ] | | `-- snvs@30370000 simple_bus [ ] | |-- aips-bus@30400000 simple_bus [ ] | `-- aips-bus@30800000 i2c [ ] | |-- i2c@30a20000 i2c [ ] | `-- i2c@30a40000 simple_bus [ ] `-- regulators => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 08 50 => i2c md 8 31 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* driver/i2c/mxc: Enable I2C bus 3 and 4York Sun2015-04-231-3/+14
| | | | | | | | | Some SoCs have more than two I2C busses. Instead of adding ifdef to the driver, macros are put into board header file where CONFIG_SYS_I2C_MXC is defined. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
* i2c:mxc fix array size of i2c_dataPeng Fan2015-01-081-11/+11
| | | | | | | | | | | We should not hardcode array size of i2c_data to 3. To CONFIG_FSL_LSCH3, there are 4 i2c interface, but not 3. So the size of i2c_data array should be calculated using "ARRAY_SIZE(i2c_bases)". To avoid compile error, move i2c_bases before sram_data structure which contains i2c_data array. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ls102xa: i2c: Add i2c support for LS102xAWang Huan2014-09-081-2/+2
| | | | | | | | | | | The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoCYork Sun2014-07-031-0/+5
| | | | | | | | | | | | | | Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
* driver/mxc_i2c: Move static data structure to global_dataYork Sun2014-04-291-10/+8
| | | | | | | | | This driver needs a data structure in SRAM before SDRAM is available. This is not alway the case using .data section. Moving this data structure to global_data guarantees it is writable. Signed-off-by: York Sun <yorksun@freescale.com> CC: Troy Kisky <troy.kisky@boundarydevices.com>
* i2c: mxc: move to new subsystemtrem2013-10-171-59/+78
| | | | Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
* Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2013-07-241-7/+55
|\ | | | | | | | | | | | | | | | | | | | | The sandburst-specific i2c drivers have been deleted, conflict was just over the SPDX conversion. Conflicts: board/sandburst/common/ppc440gx_i2c.c board/sandburst/common/ppc440gx_i2c.h Signed-off-by: Tom Rini <trini@ti.com>
| * I2C: mxc_i2c: Add support for Vybrid VF610 platformAlison Wang2013-07-231-7/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Vybrid VF610 platform. There are some differences between i.MX6 and Vybrid for I2C controller. (1) The registers' offset are different. (2) The I2C clock divider values are different. (3) In I2C control register, the enable/disable/reset bit is inverted for Vybrid comparing to i.MX6. (4) In I2C status register, the interrupt flag bit is cleared by writing "1" for Vybrid. For i.MX6, this bit is cleared by writing "0". (5) In I2C status register, the arbitration lost flag bit is cleared by writing "1" for Vybrid. For i.MX6, this bit is cleared by writing "0". Signed-off-by: Alison Wang <b18965@freescale.com>
* | Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
|/ | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* i2c: Staticize local functions in mxc i2c driverMarek Vasut2012-12-111-2/+2
| | | | | | | | | Some functions in the MXC i2c driver were not static, fix this by making them so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* imx: Use MXC_I2C_CLK in imx i2c driverMatthias Weisser2012-10-151-2/+2
| | | | | | | | i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: Matthias Weisser <weisserm@arcor.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: finish adding CONFIG_I2C_MULTI_BUS supportTroy Kisky2012-07-311-0/+17
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: add bus recovery supportTroy Kisky2012-07-311-0/+26
| | | | | | | | | Add support for calling a function that will toggle the SCL line to return the bus to idle condition. The actual toggling function is added in a later patch. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: prep work for multiple busses supportTroy Kisky2012-07-311-21/+104
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: add i2c_regs argument to i2c_imx_stopTroy Kisky2012-07-311-12/+7
| | | | | | | This is prep work for CONFIG_I2C_MULTI_BUS. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: add retriesTroy Kisky2012-07-311-9/+27
| | | | | | | Retry unexpected hardware errors. This will not retry a received NAK. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: check for arbitration lostTroy Kisky2012-07-311-0/+7
| | | | | | | No need to continue waiting if arbitration lost. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: change slave addr if conflicts with destination.Troy Kisky2012-07-311-0/+2
| | | | | | | The i2c controller cannot be both master and slave in the same transaction. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: don't disable controller after every transactionTroy Kisky2012-07-311-15/+13
| | | | | | | This helps in a multiple bus master environment which is why I also added a wait for bus idle. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: place i2c_reset code inlineTroy Kisky2012-07-311-12/+3
| | | | | | | | imx_reset is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: place imx_start code inlineTroy Kisky2012-07-311-33/+20
| | | | | | | | imx_start is only referenced once so move to that location. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: remove redundant readTroy Kisky2012-07-311-1/+0
| | | | | | | | wait_for_sr_state returns i2sr on success so no need to read again. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: combine i2c_imx_bus_busy and i2c_imx_trx_complete into ↵Troy Kisky2012-07-311-51/+29
| | | | | | | | | | | | | | | | | | | | wait_for_sr_state Not using udelay gives a more accurate timeout. The current implementation of udelay in imx-common does not seem to wait at all for a udelay(1). Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> ---- V2: Added WATCHDOG_RESET as suggested by Marek Vasut add error message when stop fails mxc_i2c: code i2c_probe as a 0 length i2c_write Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c.c: code i2c_probe as a 0 length i2c_writeTroy Kisky2012-07-311-17/+8
| | | | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: call i2c_imx_stop on error in i2c_read/i2c_writeTroy Kisky2012-07-311-3/+7
| | | | Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* mxc_i2c: create i2c_init_transferTroy Kisky2012-07-311-26/+18
| | | | | | | | | Initial code of i2c_read and i2c_write is identical, move to subroutine. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: clear i2sr before waiting for bitTroy Kisky2012-07-311-4/+5
| | | | | | | | | | | Let's clear the sr register before waiting for bit to be set, instead of clearing it after hardware sets it. No real operational difference here, but allows combining of i2c_imx_trx_complete and i2c_imx_bus_busy in later patches. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: create tx_byte functionTroy Kisky2012-07-311-58/+24
| | | | | | | | Use tx_byte function instead of having 3 copies of the code. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: remove ifdef of CONFIG_HARD_I2CTroy Kisky2012-07-311-5/+1
| | | | | | | | This is always selected when CONFIG_I2C_MXC is selected, so it adds no value. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de>
* mxc_i2c: fix i2c_imx_stopTroy Kisky2012-07-311-1/+1
| | | | | | | | | | Instead of clearing 2 bits, all the other bits were set because '|=' was used instead of '&='. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: remove setting speed at each startTroy Kisky2012-07-111-6/+0
| | | | | | | | | | | | Other then being very weird, this code was also wrong. For example, say I set speed to 100K. I'll read back the speed as 85937. But the speed is really 85937.5, so we I reset the speed to 85937, I'll get 73660.7. After a couple of transactions my speed is now exactly 68750 so it will remain there. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* mxc_i2c: specify i2c base address in config fileTroy Kisky2012-07-111-21/+4
| | | | | | | | | The following platforms had their config files changed flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd and mx53loco. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Stefano Babic <sbabic@denx.de>
* I2C: Fix mxc_i2c.c problem on imx31_phycoreMarek Vasut2011-11-031-11/+26
| | | | | | | | | | | | | | | | | The problem was caused by a global variable being used early in the boot process. The symptoms were on imx31_phycore board, reading the environment from I2C EEPROM didn't work correctly and causes default environment to be loaded. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Heiko Schocher <hs@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stefano Babic <sbabic@denx.de>
* I2C: added I2C-2 and I2C-3 to MX35Stefano Babic2011-11-031-0/+4
| | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* I2C: Add i2c_get/set_speed() to mxc_i2c.cMarek Vasut2011-10-271-8/+23
| | | | | | | Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* I2C: mxc_i2c reworkMarek Vasut2011-09-301-133/+289
| | | | | | | | | | | | | | | | Rewrite the mxc_i2c driver. * This version is much closer to Linux implementation. * Fixes IPG_PERCLK being incorrectly used as clock source * Fixes behaviour of the driver on iMX51 * Clean up coding style a bit ;-) Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Acked-by: Jason Liu <jason.hui@linro.org> Acked-by: Heiko Schocher <hs@denx.de> Tested-by: Jason Liu <jason.hui@linro.org>
* I2C: mxc: fix compilation for MX31Stefano Babic2011-09-071-4/+1
| | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* IMX: MX31: Cleanup include files and drop nasty #ifdef in driversStefano Babic2011-04-271-6/+1
| | | | | | | | | | As exception among the i.MX processors, the i.MX31 has headers without general names (mx31-regs.h, mx31.h instead of imx-regs.h and clock.h). This requires several nasty #ifdef in the drivers to include the correct header. The patch cleans up the driver and renames the header files as for the other i.MX processors. Signed-off-by: Stefano Babic <sbabic@denx.de>
* I2C: mxc_i2c: address failure with mx35 processorStefano Babic2011-02-021-18/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is sporadic failures when more as one I2C slave is on the bus and the processor tries to communicate with more as one slave. The problem was seen on a mx35pdk (two I2C slaves, PMIC controller and CAN/RTC chip). The current driver uses the IIF bit in the status register to check if the bus is busy or not. According to the manual, this is not correct, because the IIB bit should be checked. Not only, to check if a transfer is finished must be checked the ICF bit, and this is not tested at all. This patch comes from analyse with a corresponding driver provided by Freescale as part of the LTIB tool. Comparing the two drivers, it appears that the current u-boot driver checks the wrong bits, and depending on race condition, the transfer can be successful or not. The patch gets rid also of own debug function (DPRINTF), replaced with the general debug(). Tested on Freescale mx35pdk. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* I2C: mxc_i2c: get rid of __REG accessStefano Babic2011-02-021-28/+44
| | | | | | | | | | | This driver accesses to processor's register via __REG macros, that are removed (or are planned to be removed) and replaced by C structures. This patches replaces all occurrencies of __REG macros. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mxc_i2c: Add support for the i.MX35 processorStefano Babic2011-02-021-4/+5
| | | | | | Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* mxc_i2c: add support for MX53 processorLiu Hui-R643432011-02-021-3/+18
| | | | | | This patch add I2C support for Freescale MX53 processor Signed-off-by: Jason Liu <r64343@freescale.com>
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