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path: root/drivers/ddr/fsl/arm_ddr_gen3.c
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* driver/ddr/fsl: Add support for multiple DDR clocksYork Sun2015-02-241-1/+1
| | | | | | | | | Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun <yorksun@freescale.com>
* fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-111-6/+39
| | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver/ddr/freescale: Fix DDR3 driver for ARMYork Sun2014-09-081-1/+1
| | | | | | | Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr: Change Freescale ARM DDR driver to support both big and little ↵York Sun2014-02-211-51/+52
| | | | | | | | | endian Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Add Freescale DDR driver for ARMYork Sun2013-11-251-0/+213
Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>
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