| Commit message (Collapse) | Author | Age | Files | Lines |
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PMC405 and CPCI2DP: Added firmware download and booting via pci.
Patch by Matthias Fuchs, 20 Dec 2005
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Patch by Stefan Roese, 29 Nov 2005
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Patch by John Otken, 23 Nov 2005
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On PPC44x platforms, the startup message generated in "cpu.c" only
comprised the ppc type and revision but not additional informations
like speed etc. Those speed infos where printed in the board specific
code. This new implementation now prints all CPU infos in the common
cpu specific code. No board specific code is needed anymore and
therefore removed from all current 44x implementations.
Patch by Stefan Roese, 27 Nov 2005
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- Added onboard PPC440 DDR autodetection in cpu/ppc/sdram.c
- CFG_FLASH_QUIET_TEST added to use the common CFI driver
for bank autodetection
Patch by Stefan Roese, 22 Nov 2005
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Patch by Stefan Roese, 15 Nov 2005
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Patch by Stefan Roese, 01 Nov 2005
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Patch by Stefan Roese, 20 Oct 2005
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Patch by Stefan Roese, 18 Oct 2005
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CONFIG_NET_MULTI set)
Patch by Stefan Roese, 10 Oct 2005
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Patch by James MacAulay, 07 Oct 2005
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Patch by Stefan Roese, 4 Oct 2005
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add MII routines to the au1x00 ethernet driver;
add USB ohci driver (work in progress)
Patch by Thomas Sailer, 20 Jan 2005
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ethernet port on ebony.
Patch by Stefan Roese, 7 Sep 2005
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onboard DDR)
Patch by Stefan Roese, 24 Aug 2005
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now handling all 4xx cpu's.
Patch by Stefan Roese, 16 Aug 2005
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Second serial port on 440GX now defined as a system device.
Add 'Short Etch' code for Cicada PHY within 440gx_enet.c
Patch by Travis B. Sawyer, 12 Jul 2005
Check return value of malloc in 440gx_enet.c
Patch by Travis B. Sawyer, 18 Jul 2005
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Patch by Stefan Roese, 11 Aug 2005
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Patch by Stefan Roese, 08 Aug 2005
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Patch by Yuli Barcohen, 12 Dec 2004
Minor code cleanup.
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Patch by Steven Blakeslee, 04 Aug 2005
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Patch by Stefan Roese, 04 Aug 2005
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Patch by Stefan Roese, 2 Aug 2005
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Patch by Steven Blakeslee, 27 Jul 2005
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Initialize allocated dev and private hw structures
after their respective allocation in 440gx_enet.c
* Patch by Steven Scholz, 10 Jun 2005:
Fix byteorder problems with second argument of "bootm" with
standalone images;
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Make PCI target address spaces on PMC405 and CPCI405 boards
configurable via environment variables
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- Change timer frequency for ppc 440 from 10 ms to 1 ms.
Problem found by Andrew Wozniak.
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- update the pxa-regs.h file for PXA27x chips
- add PXA27x based ADSVIX board
- add support for MMC on PXA27x processors
* Patch by Andrew E. Mileski, 28 Nov 2004:
Fix PPC4xx SPD SDRAM detection bug
* Patch by Hiroshi Ito, 26 Nov 2004:
Fix logic of "test -z" and "test -n" commands
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Add missing 440GX SDRAM Controller reset
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add support for the AMD db1550 board
* Patch by Travis Sawyer, 15 Sep 2004:
Add CONFIG_SERIAL_MULTI support for ppc4xx,
update README.serial_multi
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* Cleanup confusing use of CONFIG_ETH*ADDR - ust his only to
pre-define a MAC address; use CONFIG_HAS_ETH* to enable support for
additional ethernet addresses.
* Cleanup drivers/i82365.c - avoid duplication of code
* Fix bogus "cannot span across banks" flash error message
* Add support for CompactFlash for the CPC45 Board.
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- Added I2C support for ML300.
- Added support for ML300 to read out its environment information
stored on the EEPROM.
- Added support to use board specific parameters as part of
U-Boot's environment information.
- Updated MLD files to support configuration for new features
above.
* Patches by Travis Sawyer, 5 Aug 2004:
- Remove incorrect bridge settings for eth group 6
- Add call to setup bridge in ppc_440x_eth_initialize
- Fix ppc_440x_eth_init to reset the phy only if its the
first time through, otherwise, just check the phy for the
autonegotiated speed/duplex. This allows the use of netconsole
- only print the speed/duplex the first time the phy is reset.
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Update for PPChameleon board:
- support for SysClk @ 25MHz
- support for Silicon Motion SM712 VGA controller
- some clean ups
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* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
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(JFFS2 speed enhancements) because of using non-public
data (PHYS_FLASH_SECT_SIZE)
* Patch by Travis Sawyer, 23 Apr 2004:
Fix VSC/CIS 8201 phy descrambler interoperability timing due to
errata from Vitesse Semiconductor.
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