| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setup | Larry Johnson | 2008-03-31 | 1 | -13/+14 |
| | | | | | Signed-off-by: Larry Johnson <lrj@acm.org> | ||||
| * | ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD code | Larry Johnson | 2008-02-14 | 1 | -3/+3 |
| | | | | | Signed-off-by: Larry Johnson <lrj@acm.org> | ||||
| * | Add 440EPx DDR2 SPD DIMM support | Larry Johnson | 2007-12-27 | 1 | -0/+1254 |
| This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org> | |||||
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| Talos™ II U-Boot sources for OpenBMC | Raptor Computing Systems |
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