summaryrefslogtreecommitdiffstats
path: root/cpu/ppc4xx/denali_spd_ddr2.c
Commit message (Collapse)AuthorAgeFilesLines
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-181-11/+11
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Fix printf format warnings now visible with the updated format checkStefan Roese2008-07-101-4/+4
| | | | | | | | | This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese <sr@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-121-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Fix compilation warning in denali_spd_ddr2.cStefan Roese2008-04-291-0/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Complete remove bogus dflush()Stefan Roese2008-04-291-2/+2
| | | | | | | | | | Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CFG_MEM_TOP_HIDE to Denali SPD-based SDRAM setupLarry Johnson2008-03-311-13/+14
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD codeLarry Johnson2008-02-141-3/+3
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add 440EPx DDR2 SPD DIMM supportLarry Johnson2007-12-271-0/+1254
This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>
OpenPOWER on IntegriCloud