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* | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-12-185-42/+12048
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| * | microblaze: Do not handle watchdog and gpio in SPLMichal Simek2015-12-181-1/+2
| | | | | | | | | | | | | | | | | | watchdog and gpio are not validated for SPL that's why do not use them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | microblaze: Remove support for LL_TEMACMichal Simek2015-12-182-41/+0
| | | | | | | | | | | | | | | | | | | | | LL_TEMAC is available at big endian MB and it is not properly tested that's why the patch removes it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | ARM: zynq: Add default ps7_init_gpl.c/h for ZYBONathan Rossi2015-12-183-0/+12046
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init is generated by the Vivado 2015.3 tools using the system configuration provided by Digilent located on their website. Update the kconfig so that the defconfig is not overrided to use the custom init ps7_init_gpl target by default. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2015-12-1711-35/+35
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| * | usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut2015-12-1711-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * | usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut2015-12-1711-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
| * | usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut2015-12-1711-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-174-8/+8
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| * | | armv8/ls1043aqds/rcw: change core frequency to 1600MHzMingkai Hu2015-12-172-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Change RCW for SD boot and NAND boot. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls1043ardb/rcw: change core frequency to 1600MHzMingkai Hu2015-12-172-4/+4
| |/ / | | | | | | | | | | | | | | | | | | Change RCW for SD boot and NAND boot. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-12-164-0/+71
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| * | rockchip: Add basic support for kylin boardhuang lin2015-12-134-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | kylin board use rk3036 SOC, 512M sdram, 8G emmc. This add some basic files required to allow the board to output serial message and can run command(mmc info etc). Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-12-1414-160/+161
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| * | | armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-153-13/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8: fsl-layerscale: Rewrite reserving memory for MC and debug serverYork Sun2015-12-153-51/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8: fsl-layerscape: Make DDR non secure in MMU tablesYork Sun2015-12-155-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | arm: ls1021a: merge SoC specific code in a separate fileYao Yuan2015-12-132-87/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a soc.c file to put the code for soc special settings. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls1043ardb: Add support for >2GB memoryShaohui Xie2015-12-132-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch also expose the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2080ardb: Update DDR settings for four chip-select caseYork Sun2015-12-131-4/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | armv8/ls2080aqds: Update DDR settings for four chip-select caseYork Sun2015-12-131-4/+12
| |/ / | | | | | | | | | | | | | | | | | | When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm, and 2T timing is enabled. Signed-off-by: York Sun <yorksun@freescale.com>
* | | siemens,am33x: remove ddr3 delay workaroundEgli, Samuel2015-12-121-5/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de>
* | | stm32: Convert serial driver to DMKamil Lulko2015-12-121-1/+12
|/ / | | | | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-12-111-0/+30
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| * | imx: mx7dsabresd: Add QSPI supportPeng Fan2015-12-111-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support qspi flashes for mx7dsabresd 1. introduce pin mux settings 2. enable qspi clock 3. introduce related macro definitions Default QSPI is not enabled, since we need hardware rework to use QSPI, see SPF-28590, page 9: " QSPI signals are muxed with EPDC_D[7:0] When using QSPI: de-populate R388-R391, R396-R399 populate R392-R395, R299, R300 " After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi flashes can be deteced and read/erase/write. Log info: " => sf probe SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB => sf read 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Read: OK => sf erase 0 0x4000000 SF: 67108864 bytes @ 0x0 Erased: OK => sf write 0x80000000 0 0x4000000 device 0 whole chip SF: 67108864 bytes @ 0x0 Written: OK " Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Adrian Alonso <aalonso@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | | sunxi: Add suport for A83T HomletV2 Board by Allwinnervishnupatekar2015-12-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dts and defconfig for h8homletv2 board. H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner. It has UART, ethernet, USB, HDMI, etc ports on it. A83T patches are tested on this board. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: power: enabled support for axp818vishnupatekar2015-12-101-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Add Machine Support for A83T SOCvishnupatekar2015-12-101-1/+8
|/ / | | | | | | | | | | | | | | | | | | | | Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | x86: Remove HAVE_ACPI_RESUMEBin Meng2015-12-092-2/+0
| | | | | | | | | | | | | | | | | | These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: Remove CPU_INTEL_SOCKET_RPGA989Bin Meng2015-12-092-2/+0
| | | | | | | | | | | | | | | | | | | | This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: Clean up ivybridge/chrome Kconfig optionsBin Meng2015-12-092-2/+0
| | | | | | | | | | | | | | | | | | | | There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-12-072-77/+0
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| * | zynq: sdhci: Move driver to DMMichal Simek2015-12-072-39/+0
| | | | | | | | | | | | | | | | | | | | | Move driver to DM Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | net: gem: Move driver to DMMichal Simek2015-12-072-38/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Enable DM_ETH by default for Zynq and ZynqMP - Remove board_eth_init code - Change miiphy_read function to return value instead of error code based on DM requirement - Do not enable EMIO DT support by default Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | arm: socfpga: Add SoCFPGA SR1500 boardStefan Roese2015-12-077-0/+1362
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SR1500 board is a CycloneV based board, similar to the EBV SoCrates, equipped with the following devices: - SPI NOR - eMMC - Ethernet Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
* | rpi: add support for Raspberry Pi ZeroStephen Warren2015-12-051-0/+5
| | | | | | | | | | | | | | For U-Boot's purposes, at present all we care about is ensuring there's a model table entry. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | rpi: fix revision scheme parsingStephen Warren2015-12-051-34/+53
| | | | | | | | | | | | | | | | | | | | The RPi has two different schemes for encoding board revision values. When adding RPi 2 support, I thought that the conflicting type field values were to be interpreted based on bcm2835-vs-bcm2836. In fact, the scheme bit determines the encoding. The RPi Zero uses the bcm2835 yet uses the new encoding scheme. Fix the code to cater for this correctly. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | rpi: get rid of BCM2835_BOARD_REV_* macrosStephen Warren2015-12-051-19/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two numbering schemes for the RPi revision values; old and new scheme. The values within each scheme overlap. Hence, it doesn't make sense to have absolute/global names for the revision IDs. Get rid of the names and just use the raw revision/type values to set up the array of per-revision data. This change makes most sense when coupled with the next change. However, it's split out so that the mechanical cut/paste is separate from the logic changes for easier review and problem bisection. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
* | Change e-mail address of Kamil LulkoKamil Lulko2015-12-053-3/+3
| | | | | | | | Signed-off-by: Kamil Lulko <kamil.lulko@gmail.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-12-046-257/+600
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| * arm: imx6: novena, gw_ventana: Fix use of pfuze100 bit definitionsMarek Vasut2015-12-012-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch changed the PFUZE100 swbst register bit definitions and broke PMIC configuration on multiple boards, at least on the novena and gw_ventana. This patch fixes it. commit 8fa46350a4c7dca7710362f6c871098557b934ad Author: Peng Fan <Peng.Fan@freescale.com> Date: Fri Aug 7 16:43:45 2015 +0800 power: regulator: add pfuze100 support Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Tim Harvey <tharvey@gateworks.com>
| * colibri_vf: Add board_usb_phy_mode functionSanchayan Maity2015-11-251-1/+32
| | | | | | | | | | | | | | | | Add board_usb_phy_mode function for detecting whether a port is being used as host or client using a GPIO. On Colibri Vybrid we provide GPIO 102 for this very same purpose. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
| * cgtqmx6eval: Add SPL supportOtavio Salvador2015-11-253-258/+541
| | | | | | | | | | | | | | | | | | Congatec has several MX6 boards based on quad, dual, dual-lite and solo. Add SPL support so that all the variants can be supported Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
| * cgtqmx6eval: Add SPI NOR flash supportOtavio Salvador2015-11-251-0/+29
| | | | | | | | | | | | | | | | | | | | Add SPI NOR support: => sf probe SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* | rockchip: Add basic support for evb-rk3036 boardhuang lin2015-12-014-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This add some basic files required to allow the board to dispaly serial message and can run command(mmc info etc) Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Moved board Kconfig fragment from previous patch into this one to fix build error: Signed-off-by: Simon Glass <sjg@chromium.org> Series-changes: 8 - moved board Kconfig fragment from previous patch into this one
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-11-304-0/+313
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| * | arm: atmel: Add SAMA5D2 Xplained boardWenyou Yang2015-11-304-0/+313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board supports following features: - Boot media support: SD card/e.MMC/SPI flash, - Support LCD display (optional, disabled by default), - Support ethernet, - Support USB mass storage. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> [fix checkpatch warnings] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-11-3043-124/+1400
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| * | | board/ls2080qds: Fix typo in README for QSGMII riser cardPrabhakar Kushwaha2015-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DPMACx to PHY mapping for SGMII is mentioned as QSGMII. So fix typo in README for QSGMII rise card. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: Change from ls2085aqds to ls2080aqds] Reviewed-by: York Sun <yorksun@freescale.com>
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